diff options
Diffstat (limited to 'src/mainboard/google/butterfly')
| -rw-r--r-- | src/mainboard/google/butterfly/devicetree.cb | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 5ff7f9da98..24d973e209 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -21,9 +21,9 @@ chip northbridge/intel/sandybridge register "max_mem_clock_mhz" = "666" # DDR3-1333 device domain 0 on - device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -48,27 +48,27 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug) - device pci 1c.1 on end # PCIe Port #2 (ETH0) - device pci 1c.2 on end # PCIe Port #3 (Card Reader) + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug) + device ref pcie_rp2 on end # PCIe Port #2 (ETH0) + device ref pcie_rp3 on end # PCIe Port #3 (Card Reader) #force ASPM for PCIe bridge to Card Reader register "pcie_aspm[2]" = "0x3" - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on #LPC bridge chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -78,10 +78,10 @@ chip northbridge/intel/sandybridge end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end |