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-rw-r--r--src/mainboard/google/brya/variants/kuldax/overridetree.cb6
-rw-r--r--src/mainboard/google/brya/variants/kuldax/ramstage.c9
2 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb
index 6168b2fd22..41a9e28198 100644
--- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb
@@ -51,6 +51,12 @@ chip soc/intel/alderlake
[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
+ register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+ .tdp_pl1_override = 15,
+ .tdp_pl2_override = 55,
+ .tdp_pl4 = 100,
+ }"
+
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
diff --git a/src/mainboard/google/brya/variants/kuldax/ramstage.c b/src/mainboard/google/brya/variants/kuldax/ramstage.c
index 5a7123789a..2062383e32 100644
--- a/src/mainboard/google/brya/variants/kuldax/ramstage.c
+++ b/src/mainboard/google/brya/variants/kuldax/ramstage.c
@@ -16,6 +16,9 @@ const struct cpu_power_limits limits[] = {
{ PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 },
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 140000 },
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 },
+ { PCI_DID_INTEL_RPL_P_ID_5, 15, 15000, 15000, 55000, 55000, 100000 },
+ { PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 15000, 55000, 55000, 100000 },
+ { PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 15000, 55000, 55000, 100000 },
};
const struct system_power_limits sys_limits[] = {
@@ -25,6 +28,9 @@ const struct system_power_limits sys_limits[] = {
{ PCI_DID_INTEL_ADL_P_ID_6, 15, 225 },
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 225 },
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 225 },
+ { PCI_DID_INTEL_RPL_P_ID_5, 15, 138 },
+ { PCI_DID_INTEL_RPL_P_ID_4, 15, 138 },
+ { PCI_DID_INTEL_RPL_P_ID_3, 15, 138 },
};
const struct system_power_limits revise_sys_limits[] = {
@@ -34,6 +40,9 @@ const struct system_power_limits revise_sys_limits[] = {
{ PCI_DID_INTEL_ADL_P_ID_6, 15, 225 },
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 225 },
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 225 },
+ { PCI_DID_INTEL_RPL_P_ID_5, 15, 138 },
+ { PCI_DID_INTEL_RPL_P_ID_4, 15, 138 },
+ { PCI_DID_INTEL_RPL_P_ID_3, 15, 138 },
};
/*