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-rw-r--r--src/mainboard/google/brya/variants/baseboard/devicetree.cb5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index 5b2ec14388..ce692133a0 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -20,11 +20,6 @@ chip soc/intel/alderlake
# DPTF enable
register "dptf_enable" = "1"
- register "power_limits_config" = "{
- .tdp_pl1_override = 15,
- .tdp_pl2_override = 55,
- }"
-
# Enable heci communication
register "HeciEnabled" = "1"