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-rw-r--r--src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb5
-rw-r--r--src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb5
2 files changed, 4 insertions, 6 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index b6dbf4dc5b..162796159e 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -1,7 +1,6 @@
chip soc/intel/alderlake
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+
+ device cpu_cluster 0 on end
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_A"
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index aa72ae1725..3591a7b29b 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -1,7 +1,6 @@
chip soc/intel/alderlake
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+
+ device cpu_cluster 0 on end
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"