diff options
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 3 |
2 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 346b98eef2..a36c849779 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -17,9 +17,6 @@ chip soc/intel/alderlake # DPTF enable register "dptf_enable" = "1" - # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi BT register "CnviBtCore" = "true" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 7323b106c7..ee0fbce406 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -19,9 +19,6 @@ chip soc/intel/alderlake register "tcc_offset" = "10" # TCC of 90 - # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi BT register "CnviBtCore" = "true" |