diff options
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index ce692133a0..8137df30fa 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -46,12 +46,6 @@ chip soc/intel/alderlake register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 - # TODO(b/184324979): Workaround to enable TCSS ports. FSP v2081 - # uses port enable for south XHCI ports to determine if TCSS - # ports should be enabled. Until FSP is fixed, enable south - # XHCI ports 1 and 2. - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" |