2 files changed, 81 insertions, 9 deletions

diff --git a/src/mainboard/google/brya/variants/nivviks/fw_config.c b/src/mainboard/google/brya/variants/nivviks/fw_config.c
index d899750009..6d8bab3ea8 100644
--- a/src/mainboard/google/brya/variants/nivviks/fw_config.c
+++ b/src/mainboard/google/brya/variants/nivviks/fw_config.c
@@ -1,11 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/gpio.h>
+#include <boardid.h>
 #include <bootstate.h>
 #include <console/console.h>
 #include <fw_config.h>
 
-static const struct pad_config lte_disable_pads[] = {
+static const struct pad_config lte_disable_pads_nivviks[] = {
 	/* A8  : WWAN_RF_DISABLE_ODL */
 	PAD_NC(GPP_A8, NONE),
 	/* D6  : WWAN_EN */
@@ -18,6 +19,19 @@ static const struct pad_config lte_disable_pads[] = {
 	PAD_NC(GPP_H23, NONE),
 };
 
+static const struct pad_config lte_disable_pads_nirwen[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_NC(GPP_A8, NONE),
+	/* E13  : WWAN_EN */
+	PAD_NC(GPP_E13, NONE),
+	/* F12 : WWAN_RST_L */
+	PAD_NC(GPP_F12, NONE),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_NC(GPP_H19, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_NC(GPP_H23, NONE),
+};
+
 static const struct pad_config sd_disable_pads[] = {
 	/* D8  : SD_CLKREQ_ODL */
 	PAD_NC(GPP_D8, NONE),
@@ -45,8 +59,19 @@ static const struct pad_config wfc_disable_pads[] = {
 static void fw_config_handle(void *unused)
 {
 	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
-		printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n");
-		gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
+		if (board_id() == 2) {
+			printk(BIOS_INFO, "Disable LTE-related GPIO pins on nirwen.\n");
+			gpio_configure_pads(
+				lte_disable_pads_nirwen,
+				ARRAY_SIZE(lte_disable_pads_nirwen)
+			);
+		} else {
+			printk(BIOS_INFO, "Disable LTE-related GPIO pins on nivviks.\n");
+			gpio_configure_pads(
+				lte_disable_pads_nivviks,
+				ARRAY_SIZE(lte_disable_pads_nivviks)
+			);
+		}
 	}
 
 	if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) {
diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c
index 6bb37b1b8c..2eceb8661a 100644
--- a/src/mainboard/google/brya/variants/nivviks/gpio.c
+++ b/src/mainboard/google/brya/variants/nivviks/gpio.c
@@ -6,7 +6,7 @@
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>
 
-/* Pad configuration in ramstage */
+/* Pad configuration in ramstage for nivviks board_id = 0 */
 static const struct pad_config board_id0_overrides[] = {
 	/* R4 : I2S2_SCLK ==> I2S_SPK_BCLK_R */
 	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),
@@ -30,7 +30,15 @@ static const struct pad_config board_id0_overrides[] = {
 	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
 };
 
-/* Early pad configuration in bootblock */
+/* Pad configuration in ramstage for nirwen */
+static const struct pad_config override_gpio_table_nirwen[] = {
+	/* D6  : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	/* E13  : SRCCLKREQ1# ==> WWAN_EN */
+	PAD_CFG_GPO(GPP_E13, 1, DEEP),
+};
+
+/* Early pad configuration in bootblock for nivviks */
 static const struct pad_config early_gpio_table[] = {
 	/* F12 : GSXDOUT ==> WWAN_RST_L */
 	PAD_CFG_GPO(GPP_F12, 0, DEEP),
@@ -56,6 +64,32 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPP_H13, 1, DEEP),
 };
 
+/* Early pad configuration in bootblock for nirwen */
+static const struct pad_config early_gpio_table_nirwen[] = {
+	/* F12 : GSXDOUT ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	/* E13  : SRCCLKREQ1# ==> WWAN_EN */
+	PAD_CFG_GPO(GPP_E13, 1, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+};
+
 static const struct pad_config romstage_gpio_table[] = {
 	/* H12 : UART0_RTS# ==> SD_PERST_L */
 	PAD_CFG_GPO(GPP_H12, 1, DEEP),
@@ -69,14 +103,27 @@ const struct pad_config *variant_gpio_override_table(size_t *num)
 		return board_id0_overrides;
 	}
 
-	*num = 0;
-	return NULL;
+	if (id == 1) {
+		*num = 0;
+		return NULL;
+	}
+
+	/* board_id >= 2 means nirwen */
+	*num = ARRAY_SIZE(override_gpio_table_nirwen);
+	return override_gpio_table_nirwen;
 }
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
 {
-	*num = ARRAY_SIZE(early_gpio_table);
-	return early_gpio_table;
+	const uint32_t id = board_id();
+	if (id == BOARD_ID_UNKNOWN || id < 2) {
+		*num = ARRAY_SIZE(early_gpio_table);
+		return early_gpio_table;
+	}
+
+	/* board_id >= 2 means nirwen */
+	*num = ARRAY_SIZE(early_gpio_table_nirwen);
+	return early_gpio_table_nirwen;
 }