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-rw-r--r--src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index 2ce9a7d68d..9267e21557 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -22,6 +22,9 @@ chip soc/intel/alderlake
# S0ix enable
register "s0ix_enable" = "1"
+ # DPTF enable
+ register "dptf_enable" = "1"
+
# Enable CNVi BT
register "cnvi_bt_core" = "true"