diff options
Diffstat (limited to 'src/mainboard/google/auron/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/auron/dsdt.asl | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 76998ba670..1c10f80da3 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. + * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,8 +18,6 @@ * Foundation, Inc. */ -#define ENABLE_TPM - DefinitionBlock( "dsdt.aml", "DSDT", @@ -30,23 +28,22 @@ DefinitionBlock( ) { // Some generic macros - #include "acpi/platform.asl" - #include "acpi/mainboard.asl" + #include <soc/intel/broadwell/acpi/platform.asl> // global NVS and variables - #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <soc/intel/broadwell/acpi/globalnvs.asl> // General Purpose Events //#include "acpi/gpe.asl" // CPU - #include <cpu/intel/haswell/acpi/cpu.asl> + #include <soc/intel/broadwell/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> + #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <soc/intel/broadwell/acpi/pch.asl> } } @@ -58,5 +55,8 @@ DefinitionBlock( #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + #include <soc/intel/broadwell/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" } |