diff options
Diffstat (limited to 'src/mainboard/gizmosphere/gizmo/romstage.c')
| -rw-r--r-- | src/mainboard/gizmosphere/gizmo/romstage.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 972f5d0f6a..e6276ff04e 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -47,17 +47,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; msr_t msr; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - msr.lo = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) & 0xFFFFFFFF; - msr.hi = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) >> 32; - wrmsr (MSR_MTRR_VARIABLE_BASE6, msr); - - msr.lo = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) & 0xFFFFFFFF; - msr.hi = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) >> 32; - wrmsr (MSR_MTRR_VARIABLE_MASK6, msr); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ msr.lo = 0; |