diff options
Diffstat (limited to 'src/mainboard/gigabyte')
| -rw-r--r-- | src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c | 64 |
1 files changed, 6 insertions, 58 deletions
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index cd1345148d..467a66f959 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -14,25 +14,17 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <cpu/x86/lapic.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> -#include <console/console.h> -#include <arch/romstage.h> #include <northbridge/intel/i945/i945.h> -#include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/pmclib.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define EC_DEV PNP_DEV(0x2e, IT8718F_EC) #define SUPERIO_DEV PNP_DEV(0x2e, 0) -static void setup_sio(void) +void mainboard_superio_config(void) { /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x40); @@ -54,59 +46,15 @@ static void setup_sio(void) ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 ite_reg_write(EC_DEV, 0x30, 0xff); // Enable -} - -static void rcba_config(void) -{ - /* Enable PCIe Root Port Clock Gate */ - RCBA32(CG) = 0x00000001; -} -void mainboard_romstage_entry(void) -{ - int s3resume = 0, boot_mode = 0; - enable_lapic(); - - i82801gx_lpc_setup(); - /* Enable SuperIO PM */ - setup_sio(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* Disable SIO reboot */ ite_reg_write(GPIO_DEV, 0xEF, 0x7E); +} - /* Set up the console */ - console_init(); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected.\n"); - boot_mode = 1; - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : boot_mode, NULL); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); +void mainboard_late_rcba_config(void) +{ + /* Enable PCIe Root Port Clock Gate */ + RCBA32(CG) = 0x00000001; } |