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Diffstat (limited to 'src/mainboard/getac/p470/devicetree.cb')
| -rw-r--r-- | src/mainboard/getac/p470/devicetree.cb | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb new file mode 100644 index 0000000000..26939772ad --- /dev/null +++ b/src/mainboard/getac/p470/devicetree.cb @@ -0,0 +1,144 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i945 + + device lapic_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + # autodetect: + #device pci 01.0 off end # i945 PCIe root port + #device pci 02.0 on end # vga controller + #device pci 02.1 on end # display controller + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x0a" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0a" + register "pirqd_routing" = "0x0a" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x0a" + register "pirqh_routing" = "0x0a" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi8_routing" = "1" # EXTSMI low active + register "gpi7_routing" = "2" # ECSCI low active + + # GPE0 Enables + register "gpe0_en" = "0x00800106" + register "alt_gp_smi_en" = "0x0100" + + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe port 1 + device pci 1c.1 on end # PCIe port 2 + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + #device pci 1c.4 off end # PCIe port 5 + #device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on + chip southbridge/ti/pcixx12 + + end + end # PCI bridge + #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # LPC bridge + chip superio/smsc/fdc37n972 + device pnp 2e.0 off # Floppy + end + device pnp 2e.1 off # ACPI PM + end + # 2e.2 does not exist + device pnp 2e.3 off # Parallel port + end + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off + end + #device pnp 2e.6 on # RTC + # io 0x60 = 0x70 + # io 0x62 = 0x74 + #end + device pnp 2e.7 off # Keyboard + end + device pnp 2e.8 off # EC + io 0x60 = 0x62 + end + #device pnp 2e.9 on # Mailbox + #end + end + chip superio/smsc/sio10n268 + device pnp 4e.0 off # Floppy + end + device pnp 4e.1 off # Parport + end + #device pnp 4e.2 on # COM3 + # io 0x60 = 0x3e8 + # irq 0x70 = 11 + #end + #device pnp 4e.3 on # COM4 + # io 0x60 = 0x2e8 + # irq 0x70 = 10 + #end + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + end + device pnp 4e.7 off # GPIO1, GAME, MIDI + end + device pnp 4e.8 off # GPIO2 + end + device pnp 4e.9 off # GPIO3/4 + end + device pnp 4e.a off # ACPI + end + device pnp 4e.b off # HWM + end + end + + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end +end |