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-rw-r--r--src/mainboard/foxconn/d41s/Kconfig46
-rw-r--r--src/mainboard/foxconn/d41s/Kconfig.name2
-rw-r--r--src/mainboard/foxconn/d41s/Makefile.inc2
-rw-r--r--src/mainboard/foxconn/d41s/acpi/ec.asl1
-rw-r--r--src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl36
-rw-r--r--src/mainboard/foxconn/d41s/acpi/platform.asl28
-rw-r--r--src/mainboard/foxconn/d41s/acpi/superio.asl31
-rw-r--r--src/mainboard/foxconn/d41s/acpi_tables.c21
-rw-r--r--src/mainboard/foxconn/d41s/board_info.txt6
-rw-r--r--src/mainboard/foxconn/d41s/cmos.default5
-rw-r--r--src/mainboard/foxconn/d41s/cmos.layout90
-rw-r--r--src/mainboard/foxconn/d41s/cstates.c22
-rw-r--r--src/mainboard/foxconn/d41s/data.vbtbin0 -> 3730 bytes
-rw-r--r--src/mainboard/foxconn/d41s/devicetree.cb109
-rw-r--r--src/mainboard/foxconn/d41s/dsdt.asl41
-rw-r--r--src/mainboard/foxconn/d41s/gpio.c163
-rw-r--r--src/mainboard/foxconn/d41s/hda_verb.c39
-rw-r--r--src/mainboard/foxconn/d41s/mainboard.c27
-rw-r--r--src/mainboard/foxconn/d41s/romstage.c147
19 files changed, 816 insertions, 0 deletions
diff --git a/src/mainboard/foxconn/d41s/Kconfig b/src/mainboard/foxconn/d41s/Kconfig
new file mode 100644
index 0000000000..56ab34f8fd
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/Kconfig
@@ -0,0 +1,46 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_FOXCONN_D41S
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_INTEL_SOCKET_FCBGA559
+ select NORTHBRIDGE_INTEL_PINEVIEW
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_ITE_IT8721F
+ select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
+ select BOARD_ROMSIZE_KB_1024
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select INTEL_INT15
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select DRIVERS_I2C_CK505
+ select INTEL_GMA_HAVE_VBT
+
+config MAX_CPUS
+ int
+ default 4
+
+config MAINBOARD_DIR
+ string
+ default foxconn/d41s
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "D41S"
+
+endif # BOARD_FOXCONN_D41S
diff --git a/src/mainboard/foxconn/d41s/Kconfig.name b/src/mainboard/foxconn/d41s/Kconfig.name
new file mode 100644
index 0000000000..9462f94269
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_FOXCONN_D41S
+ bool "D41S, D42S, D51S, D52S"
diff --git a/src/mainboard/foxconn/d41s/Makefile.inc b/src/mainboard/foxconn/d41s/Makefile.inc
new file mode 100644
index 0000000000..f3d7e76263
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/Makefile.inc
@@ -0,0 +1,2 @@
+ramstage-y += cstates.c
+romstage-y += gpio.c
diff --git a/src/mainboard/foxconn/d41s/acpi/ec.asl b/src/mainboard/foxconn/d41s/acpi/ec.asl
new file mode 100644
index 0000000000..31eb392c8a
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/acpi/ec.asl
@@ -0,0 +1 @@
+/* Dummy file - No license required. */
diff --git a/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000000..23c39ef5f2
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 0x15},
+ Package() { 0x0000ffff, 1, 0, 0x16},
+ Package() { 0x0000ffff, 2, 0, 0x17},
+ Package() { 0x0000ffff, 3, 0, 0x14},
+ Package() { 0x0001ffff, 0, 0, 0x13},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+ })
+}
diff --git a/src/mainboard/foxconn/d41s/acpi/platform.asl b/src/mainboard/foxconn/d41s/acpi/platform.asl
new file mode 100644
index 0000000000..6c92a4ed47
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/acpi/platform.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice. */
+ Store(Arg0, PICM)
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) /* SMI Function */
+ Store (0, TRP0) /* Generate trap */
+ Return (SMIF) /* Return value of SMI handler */
+}
diff --git a/src/mainboard/foxconn/d41s/acpi/superio.asl b/src/mainboard/foxconn/d41s/acpi/superio.asl
new file mode 100644
index 0000000000..07742e88a2
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/acpi/superio.asl
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ * Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#undef IT8721F_SHOW_SP1
+#undef IT8721F_SHOW_SP2
+#undef IT8721F_SHOW_EC
+#undef IT8721F_SHOW_KBCK
+#undef IT8721F_SHOW_KBCM
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define IT8721F_SHOW_SP1
+#define IT8721F_SHOW_SP2
+#define IT8721F_SHOW_EC
+#define IT8721F_SHOW_KBCK
+#define IT8721F_SHOW_KBCM
+#include <superio/ite/it8721f/acpi/superio.asl>
diff --git a/src/mainboard/foxconn/d41s/acpi_tables.c b/src/mainboard/foxconn/d41s/acpi_tables.c
new file mode 100644
index 0000000000..92688bfc3a
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/acpi_tables.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <southbridge/intel/i82801gx/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+}
diff --git a/src/mainboard/foxconn/d41s/board_info.txt b/src/mainboard/foxconn/d41s/board_info.txt
new file mode 100644
index 0000000000..965fcdabf9
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us0000481
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/foxconn/d41s/cmos.default b/src/mainboard/foxconn/d41s/cmos.default
new file mode 100644
index 0000000000..41098be2bb
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/cmos.default
@@ -0,0 +1,5 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+gfx_uma_size=8M
diff --git a/src/mainboard/foxconn/d41s/cmos.layout b/src/mainboard/foxconn/d41s/cmos.layout
new file mode 100644
index 0000000000..9b9a084fc0
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/cmos.layout
@@ -0,0 +1,90 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: bootloader
+416 512 s 0 boot_devices
+
+# coreboot config options: cpu
+944 1 e 2 hyper_threading
+#945 7 r 0 unused
+
+# coreboot config options: northbridge
+952 3 e 11 gfx_uma_size
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+11 0 8M
+11 1 16M
+11 2 32M
+11 3 48M
+11 4 64M
+11 5 128M
+11 6 256M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/foxconn/d41s/cstates.c b/src/mainboard/foxconn/d41s/cstates.c
new file mode 100644
index 0000000000..b7eb6df341
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/cstates.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <arch/x86/include/arch/acpigen.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ return 0;
+}
diff --git a/src/mainboard/foxconn/d41s/data.vbt b/src/mainboard/foxconn/d41s/data.vbt
new file mode 100644
index 0000000000..55707378e3
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/data.vbt
Binary files differ
diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb
new file mode 100644
index 0000000000..e03a596916
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/devicetree.cb
@@ -0,0 +1,109 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+# Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/pineview # Northbridge
+ register "gfx.use_spread_spectrum_clock" = "0"
+ register "use_crt" = "1"
+ register "use_lvds" = "0"
+
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_FCBGA559 # CPU
+ device lapic 0 on end # APIC
+ end
+ end
+ device domain 0 on # PCI domain
+ device pci 0.0 on end # Host Bridge
+ device pci 1.0 off end # PEG
+ device pci 2.0 on end # Integrated graphics controller
+ device pci 2.1 off end # Integrated graphics controller 2
+ chip southbridge/intel/i82801gx # Southbridge
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x0b"
+ register "pirqc_routing" = "0x0b"
+ register "pirqd_routing" = "0x0b"
+ register "pirqe_routing" = "0x0b"
+ register "pirqf_routing" = "0x0b"
+ register "pirqg_routing" = "0x0b"
+ register "pirqh_routing" = "0x0b"
+ register "sata_ahci" = "0x1"
+ register "sata_ports_implemented" = "0x3"
+ register "gpe0_en" = "0x441"
+
+ device pci 1b.0 on end # Audio
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on end # PCIe 2 (NIC)
+ device pci 1c.2 off end # PCIe 3
+ device pci 1c.3 off end # PCIe 4
+ device pci 1d.0 on end # USB
+ device pci 1d.1 on end # USB
+ device pci 1d.2 on end # USB
+ device pci 1d.3 on end # USB
+ device pci 1d.7 on end # USB
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA bridge
+ chip superio/ite/it8721f # Super I/O
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # PP
+ io 0x60 = 0x378
+ io 0x62 = 0
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # EC
+ io 0x60 = 0xa10
+ io 0x62 = 0xa00
+ irq 0x70 = 0
+ end
+ device pnp 2e.5 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ end
+ device pnp 2e.6 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.a on # CIR
+ io 0x60 = 0x3e0
+ irq 0x70 = 10
+ end
+ end
+ end
+ device pci 1f.1 off end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on # SMbus
+ chip drivers/i2c/ck505
+ register "mask" = "{ 0x00, 0x80, 0xff, 0xff,
+ 0xff }"
+ register "regs" = "{ 0x00, 0x80, 0xfe, 0xff,
+ 0xfc }"
+ device i2c 69 on end
+ end
+ end
+ device pci 1f.4 off end
+ device pci 1f.5 off end
+ device pci 1f.6 off end
+ end
+ end
+end
diff --git a/src/mainboard/foxconn/d41s/dsdt.asl b/src/mainboard/foxconn/d41s/dsdt.asl
new file mode 100644
index 0000000000..621b87dc7a
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/dsdt.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20090419 // OEM revision
+)
+{
+ #include "acpi/platform.asl"
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+
+ #include <cpu/intel/speedstep/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/pineview/acpi/pineview.asl>
+ #include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/foxconn/d41s/gpio.c b/src/mainboard/foxconn/d41s/gpio.c
new file mode 100644
index 0000000000..e88e4db0c6
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/gpio.c
@@ -0,0 +1,163 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_NATIVE,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_NATIVE,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_NATIVE,
+ .gpio22 = GPIO_MODE_NATIVE,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_NATIVE,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_OUTPUT,
+ .gpio6 = GPIO_DIR_OUTPUT,
+ .gpio7 = GPIO_DIR_OUTPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_OUTPUT,
+ .gpio14 = GPIO_DIR_OUTPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW,
+ .gpio6 = GPIO_LEVEL_LOW,
+ .gpio7 = GPIO_LEVEL_LOW,
+ .gpio8 = GPIO_LEVEL_LOW,
+ .gpio9 = GPIO_LEVEL_LOW,
+ .gpio10 = GPIO_LEVEL_LOW,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio13 = GPIO_LEVEL_LOW,
+ .gpio14 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio25 = GPIO_LEVEL_LOW,
+ .gpio26 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_NATIVE,
+ .gpio49 = GPIO_MODE_NATIVE,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_NATIVE,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+};
diff --git a/src/mainboard/foxconn/d41s/hda_verb.c b/src/mainboard/foxconn/d41s/hda_verb.c
new file mode 100644
index 0000000000..dbe383e6f3
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/hda_verb.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0662,
+ 0x105b0d55, // Subsystem ID
+ 0x0000000a, // Number of entries
+
+ /* Pin Widget Verb Table */
+ AZALIA_PIN_CFG(0, 0x14, 0x01014c10),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19c30),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c31),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181343f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),
+ AZALIA_PIN_CFG(0, 0x1e, 0x99430120),
+};
+
+const u32 pc_beep_verbs[] = {
+};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/foxconn/d41s/mainboard.c b/src/mainboard/foxconn/d41s/mainboard.c
new file mode 100644
index 0000000000..3263f9a065
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/mainboard.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+ GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c
new file mode 100644
index 0000000000..3f81e6765b
--- /dev/null
+++ b/src/mainboard/foxconn/d41s/romstage.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/gpio.h>
+#include <northbridge/intel/pineview/raminit.h>
+#include <northbridge/intel/pineview/pineview.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <cpu/x86/lapic.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8721f/it8721f.h>
+#include <lib.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <romstage_handoff.h>
+#include <timestamp.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1)
+
+/* Early mainboard specific GPIO setup */
+static void mb_gpio_init(void)
+{
+ pci_devfn_t dev;
+
+ /* Southbridge GPIOs. */
+ dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+ /* Set the value for GPIO base address register and enable GPIO. */
+ pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
+ pci_write_config8(dev, GPIO_CNTL, 0x10);
+
+ setup_pch_gpios(&mainboard_gpio_map);
+}
+
+static void nm10_enable_lpc(void)
+{
+ /* Disable Serial IRQ */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
+ /* Decode range */
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC,
+ pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
+ | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
+ | COMA_LPC_EN);
+
+ /* Environment Controller */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01);
+}
+
+static void rcba_config(void)
+{
+ /* Set up virtual channel 0 */
+ RCBA32(0x0014) = 0x80000001;
+ RCBA32(0x001c) = 0x03128010;
+
+ /* Enable IOAPIC */
+ RCBA8(OIC) = 0x03;
+
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
+ | FD_ACAUD | FD_PATA;
+ RCBA32(FD) |= 1;
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
+ int cbmem_was_initted;
+ int s3resume = 0;
+ int boot_path;
+
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ if (bist == 0)
+ enable_lapic();
+
+ /* Disable watchdog timer */
+ RCBA32(GCS) = RCBA32(GCS) | 0x20;
+
+ /* Set southbridge and Super I/O GPIOs. */
+ mb_gpio_init();
+
+ nm10_enable_lpc();
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ report_bist_failure(bist);
+ enable_smbus();
+
+ pineview_early_initialization();
+
+ post_code(0x30);
+
+ s3resume = southbridge_detect_s3_resume();
+
+ if (s3resume) {
+ boot_path = BOOT_PATH_RESUME;
+ } else {
+ if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */
+ boot_path = BOOT_PATH_RESET;
+ else
+ boot_path = BOOT_PATH_NORMAL;
+ }
+
+ printk(BIOS_DEBUG, "Initializing memory\n");
+ timestamp_add_now(TS_BEFORE_INITRAM);
+ sdram_initialize(boot_path, spd_addrmap);
+ timestamp_add_now(TS_AFTER_INITRAM);
+ printk(BIOS_DEBUG, "Memory initialized\n");
+
+ post_code(0x31);
+
+ quick_ram_check();
+
+ rcba_config();
+
+ cbmem_was_initted = !cbmem_recovery(s3resume);
+
+ if (!cbmem_was_initted && s3resume) {
+ /* Failed S3 resume, reset to come up cleanly */
+ outb(0x6, 0xcf9);
+ halt();
+ }
+
+ romstage_handoff_init(s3resume);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 09:11:07 +0000