diff options
Diffstat (limited to 'src/mainboard/emulation/qemu-riscv')
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/Kconfig | 97 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/Makefile.inc | 19 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/board_info.txt | 2 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/bootblock.c | 45 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/devicetree.cb | 20 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/mainboard.c | 34 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/romstage.c | 29 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/uart.c | 60 |
8 files changed, 306 insertions, 0 deletions
diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig new file mode 100644 index 0000000000..d7d5cc984c --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -0,0 +1,97 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +# To execute, do: +# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom + +if BOARD_EMULATION_QEMU_UCB_RISCV + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_UCB_RISCV + select BOARD_ROMSIZE_KB_4096 + select ARCH_BOOTBLOCK_RISCV + select HAVE_UART_SPECIAL + +config MAINBOARD_DIR + string + default emulation/qemu-riscv + +config MAINBOARD_PART_NUMBER + string + default "QEMU RISCV" + +config MAX_CPUS + int + default 1 + +config MAINBOARD_VENDOR + string + default "UCB" + +config DRAM_SIZE_MB + int + default 32768 + +# Memory map for qemu riscv +# +# 0x0000_0000: jump instruction (by qemu) +# 0x0002_0000: bootblock (entry of kernel / firmware) +# 0x0003_0000: romstage, assume up to 128KB in size. +# 0x0007_ff00: stack pointer +# 0x0010_0000: CBFS header +# 0x0011_0000: CBFS data +# 0x0100_0000: reserved for ramstage + +config BOOTBLOCK_BASE + hex + default 0x00000000 + +config ROMSTAGE_BASE + hex + default 0x00020000 + +config RAMSTAGE_BASE + hex + default 0x100000 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x10000 + +config CBFS_ROM_OFFSET + hex + default 0x10040 + +config RAMTOP + hex + default 0x1000000 + +config STACK_TOP + hex + default 0x0007ff00 + +config STACK_BOTTOM + hex + default 0x00040000 + +config STACK_SIZE + hex + default 0x0003ff00 + +endif # BOARD_EMULATION_QEMU_UCB_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc new file mode 100644 index 0000000000..bc01d2f6cf --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +bootblock-y += bootblock.c +bootblock-y += uart.c +romstage-y += romstage.c +romstage-y += uart.c +ramstage-y += uart.c diff --git a/src/mainboard/emulation/qemu-riscv/board_info.txt b/src/mainboard/emulation/qemu-riscv/board_info.txt new file mode 100644 index 0000000000..811e8e0840 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/board_info.txt @@ -0,0 +1,2 @@ +Board name: QEMU RISCV +Category: emulation diff --git a/src/mainboard/emulation/qemu-riscv/bootblock.c b/src/mainboard/emulation/qemu-riscv/bootblock.c new file mode 100644 index 0000000000..831b193a6e --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/bootblock.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/exception.h> +#include <arch/hlt.h> +#include <bootblock_common.h> +#include <cbfs.h> +#include <console/console.h> +#include <arch/stages.h> + +// the qemu part of all this is very, very non-hardware like. +// so it gets its own bootblock. +void main(void) +{ + void *entry; + + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + console_init(); + exception_init(); + } + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX"/romstage"); + if (! entry) { + printk(BIOS_EMERG, "AAAAAAAAAAAAAA no romstage!\n"); + while (1); + } + + stage_exit(entry); +} diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb new file mode 100644 index 0000000000..e3ce08829e --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +chip soc/ucb/riscv + device cpu_cluster 0 on end + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c new file mode 100644 index 0000000000..111e9b185b --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <cbmem.h> + +static void mainboard_enable(device_t dev) +{ + + if (!dev) { + printk(BIOS_EMERG, "No dev0; die\n"); + while (1); + } + + ram_resource(dev, 0, 2048, 32768); + cbmem_recovery(0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/mainboard/emulation/qemu-riscv/romstage.c new file mode 100644 index 0000000000..f4b44f614c --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/romstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <arch/stages.h> + +void main(void) +{ + void *entry; + + console_init(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX"/ramstage"); + + stage_exit(entry); +} diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c new file mode 100644 index 0000000000..40192c91fa --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console/uart.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include "frontend.h" + +static uint8_t *buf = (void *)0x3f8; +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t) buf; +} + +void uart_init(int idx) +{ +} + +unsigned char uart_rx_byte(int idx) +{ + return *buf; +} + +void uart_tx_byte(int idx, unsigned char data) +{ + *buf = data; +} + +void uart_tx_flush(int idx) +{ +} + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = 0x3f8; + serial.baud = 115200; + lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif |