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+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config BOARD_EAGLELION_5BCM
+ bool "5BCM"
+ select ARCH_X86
+ select CPU_AMD_GX1
+ select NORTHBRIDGE_AMD_GX1
+ select SOUTHBRIDGE_AMD_CS5530
+ select SUPERIO_NSC_PC97317
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config MAINBOARD_DIR
+ string
+ default eaglelion/5bcm
+ depends on BOARD_EAGLELION_5BCM
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "5BCM"
+ depends on BOARD_EAGLELION_5BCM
+
+config HAVE_OPTION_TABLE
+ bool
+ default n
+ depends on BOARD_EAGLELION_5BCM
+
+config IRQ_SLOT_COUNT
+ int
+ default 2
+ depends on BOARD_EAGLELION_5BCM
+