diff options
Diffstat (limited to 'src/mainboard/densitron')
| -rw-r--r-- | src/mainboard/densitron/dpx114/Config.lb | 172 | ||||
| -rw-r--r-- | src/mainboard/densitron/dpx114/auto.c | 38 | ||||
| -rw-r--r-- | src/mainboard/densitron/dpx114/chip.h | 2 | ||||
| -rw-r--r-- | src/mainboard/densitron/dpx114/failover.c | 37 | ||||
| -rw-r--r-- | src/mainboard/densitron/dpx114/mainboard.c | 30 |
5 files changed, 91 insertions, 188 deletions
diff --git a/src/mainboard/densitron/dpx114/Config.lb b/src/mainboard/densitron/dpx114/Config.lb index 0450b2b1b9..05698b117d 100644 --- a/src/mainboard/densitron/dpx114/Config.lb +++ b/src/mainboard/densitron/dpx114/Config.lb @@ -1,86 +1,3 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE -uses CONFIG_ROM_STREAM -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses CONFIG_ROM_STREAM_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE - -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default HAVE_MP_TABLE=0 - -## -## Build code to reset the motherboard from linuxBIOS -## -default HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=5 -object irq_tables.o - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=1 - -### -### LinuxBIOS layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -default ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 - ## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. @@ -99,7 +16,6 @@ end ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_STREAM = 1 ## ## Compute where this copy of linuxBIOS will start in the boot rom @@ -126,49 +42,49 @@ arch i386 end ## Build the objects we have code for in this directory. ## - driver mainboard.o +if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c" - action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "./failover.E ./romcc" - action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E" + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c" - action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "./auto.E ./romcc" - action "./romcc -O -mcpu=c3 ./auto.E " + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## -mainboardinit cpu/i386/entry16.inc -mainboardinit cpu/i386/entry32.inc -ldscript /cpu/i386/entry16.lds -ldscript /cpu/i386/entry32.lds +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where linuxBIOS is entered) ## if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds else - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds end ### Should this be in the northbridge code? @@ -180,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -## -## Setup our mtrrs -## -# mainboardinit cpu/p6/earlymtrr.inc - ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should @@ -202,7 +113,10 @@ end ## ## Setup RAM ## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc ## ## Include the secondary Configuration files @@ -210,32 +124,24 @@ mainboardinit ./auto.inc dir /pc80 config chip.h -northbridge via/vt8601 "vt8601" -# pci 0:0.0 -# pci 0:1.0 - southbridge via/vt8231 "vt8231" -# pci 0:11.0 -# pci 0:11.1 -# pci 0:11.2 -# pci 0:11.3 -# pci 0:11.4 -# pci 0:11.5 -# pci 0:11.6 -# pci 0:12.0 - register "enable_usb" = "0" - register "enable_native_ide" = "0" - register "enable_com_ports" = "1" - register "enable_keyboard" = "0" - register "enable_nvram" = "1" +chip northbridge/via/vt8601 + device pci_domain 0 on + chip southbridge/via/vt8231 + register "enable_usb" = "0" + register "enable_native_ide" = "0" + register "enable_com_ports" = "1" + register "enable_keyboard" = "0" + register "enable_nvram" = "1" +# device pci 0:11.0 on end +# device pci 0:11.1 on end +# device pci 0:11.2 on end +# device pci 0:11.3 on end +# device pci 0:11.4 on end +# device pci 0:11.5 on end +# device pci 0:11.6 on end +# device pci 0:12.0 on end + end + end + chip cpu/via/model_centaur end end - -cpu p6 "cpu0" - -end - -## -## Include the old serial code for those few places that still need it. -## -mainboardinit pc80/serial.inc -mainboardinit arch/i386/lib/console.inc diff --git a/src/mainboard/densitron/dpx114/auto.c b/src/mainboard/densitron/dpx114/auto.c index 7b1c637cd0..a1b3818b93 100644 --- a/src/mainboard/densitron/dpx114/auto.c +++ b/src/mainboard/densitron/dpx114/auto.c @@ -2,7 +2,9 @@ #include <stdint.h> #include <device/pci_def.h> -#include <cpu/p6/apic.h> +#if 0 +#include <cpu/x86/lapic.h> +#endif #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> @@ -11,7 +13,8 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "northbridge/via/vt8601/raminit.h" -#include "cpu/p6/earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" /* */ @@ -23,10 +26,22 @@ void udelay(int usecs) } #include "lib/delay.c" -#include "cpu/p6/boot_cpu.c" +#include "cpu/x86/lapic/boot_cpu.c" #include "debug.c" +#include "southbridge/via/vt8231/vt8231_early_smbus.c" + + #include "southbridge/via/vt8231/vt8231_early_serial.c" +static inline int spd_read_byte(unsigned device, unsigned address) +{ + unsigned char c; + c = smbus_read_byte(device, address); + return c; +} + +#include "northbridge/via/vt8601/raminit.c" + static void enable_mainboard_devices(void) { @@ -68,16 +83,22 @@ static void enable_shadow_ram(void) pci_write_config8(dev, 0x63, shadowreg); } -static void main(void) +static void main(unsigned long bist) { unsigned long x; - /* init_timer();*/ - outb(5, 0x80); - - enable_vt8231_serial(); + if (bist == 0) { + early_mtrr_init(); + } + enable_vt8231_serial(); uart_init(); console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + /* init_timer();*/ + outb(5, 0x80); enable_mainboard_devices(); enable_smbus(); @@ -102,5 +123,4 @@ static void main(void) ram_check(check_addrs[i].lo, check_addrs[i].hi); } #endif - early_mtrr_init(); } diff --git a/src/mainboard/densitron/dpx114/chip.h b/src/mainboard/densitron/dpx114/chip.h index 8f7eae8bee..10beb176b0 100644 --- a/src/mainboard/densitron/dpx114/chip.h +++ b/src/mainboard/densitron/dpx114/chip.h @@ -1,4 +1,4 @@ -extern struct chip_operations mainboard_densitron_dpx114_control; +extern struct chip_operations mainboard_densitron_dpx114_ops; struct mainboard_densitron_dpx114_config { int nothing; diff --git a/src/mainboard/densitron/dpx114/failover.c b/src/mainboard/densitron/dpx114/failover.c index bd0df4e89d..bdcb9eaed2 100644 --- a/src/mainboard/densitron/dpx114/failover.c +++ b/src/mainboard/densitron/dpx114/failover.c @@ -5,25 +5,28 @@ #include <arch/io.h> #include "arch/romcc_io.h" #include "pc80/mc146818rtc_early.c" -#include "cpu/p6/boot_cpu.c" -static void main(void) +static unsigned long main(unsigned long bist) { - /* for now, just always assume failure */ - -#if 0 - /* Is this a cpu reset? */ - if (cpu_init_detected()) { - if (last_boot_normal()) { - asm("jmp __normal_image"); - } else { - asm("jmp __cpu_reset"); - } - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - asm("jmp __normal_image"); + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; } -#endif + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; } diff --git a/src/mainboard/densitron/dpx114/mainboard.c b/src/mainboard/densitron/dpx114/mainboard.c index 188da9216e..f973012ca0 100644 --- a/src/mainboard/densitron/dpx114/mainboard.c +++ b/src/mainboard/densitron/dpx114/mainboard.c @@ -3,35 +3,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> - -#include <arch/io.h> #include "chip.h" -static int -mainboard_scan_bus(device_t root, int maxbus) -{ - int retval; - printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus); - retval = pci_scan_bus(root->bus, 0, 0xff, maxbus); - printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus); - return maxbus; -} - -static struct device_operations mainboard_operations = { - .read_resources = root_dev_read_resources, - .set_resources = root_dev_set_resources, - .enable_resources = root_dev_enable_resources, - .init = root_dev_init, - .scan_bus = mainboard_scan_bus, - .enable = 0, -}; - -static void enable_dev(device_t dev) -{ - dev->ops = &mainboard_operations; -} -struct chip_operations mainboard_via_epia_control = { - .enable_dev = enable_dev, - .name = "VIA EPIA mainboard ", +struct chip_operations mainboard_densitron_dpx114_ops = { + CHIP_NAME("Densitron DPX114 mainboard ") }; |