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-rw-r--r--src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb4
-rw-r--r--src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb4
-rw-r--r--src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb1
3 files changed, 2 insertions, 7 deletions
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
index ce683b37dc..a98d144147 100644
--- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
+++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
@@ -55,9 +55,7 @@ chip soc/intel/cannonlake
register "gpe0_dw2" = "PMC_GPP_E"
# Actual device tree
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+ device cpu_cluster 0 on end
device domain 0 on
subsystemid 0x1558 0x1401 inherit
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
index d22f57419a..765d17c471 100644
--- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
@@ -35,9 +35,7 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
}"
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+ device cpu_cluster 0 on end
device domain 0 on
subsystemid 0x1558 0x1313 inherit
device ref system_agent on end
diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb
index e194ba6473..73f32e3a5d 100644
--- a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb
+++ b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb
@@ -2,7 +2,6 @@ chip soc/intel/tigerlake
device cpu_cluster 0 on
register "tcc_offset" = "12"
register "eist_enable" = "true"
- device lapic 0 on end
end
device domain 0 on
subsystemid 0x1558 0x14a1 inherit