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-rw-r--r--src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb31
1 files changed, 0 insertions, 31 deletions
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
index a223b7e529..6a4f97d0f6 100644
--- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
@@ -46,9 +46,7 @@ chip soc/intel/skylake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
- device pci 05.0 off end # Imaging Unit
device pci 08.0 on end # Gaussian Mixture Model
- device pci 13.0 off end # Sensor Hub
device pci 14.0 on # USB xHCI
register "SsicPortEnable" = "0"
# USB2
@@ -65,20 +63,10 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left
end
- device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
- device pci 14.3 off end # Camera
- device pci 15.0 off end # I2C0
- device pci 15.1 off end # I2C1
- device pci 15.2 off end # I2C2
- device pci 15.3 off end # I2C3
device pci 16.0 on # Management Engine Interface 1
register "HeciEnabled" = "1"
end
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on # SATA
register "SataSalpSupport" = "0"
# Ports
@@ -87,8 +75,6 @@ chip soc/intel/skylake
register "SataPortsDevSlp[2]" = "1"
end
device pci 19.0 on end # UART 2
- device pci 19.1 off end # I2C5
- device pci 19.2 off end # I2C4
device pci 1c.0 on # PCI Express Port 1
device pci 00.0 on end # x4 TBT
register "PcieRpEnable[0]" = "1"
@@ -99,9 +85,6 @@ chip soc/intel/skylake
register "PcieRpLtrEnable[0]" = "1"
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X"
end
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 on # PCI Express Port 5
device pci 00.0 on end # x1 LAN
register "PcieRpEnable[4]" = "1"
@@ -119,8 +102,6 @@ chip soc/intel/skylake
register "PcieRpLtrEnable[5]" = "1"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
end
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on # PCI Express Port 9
device pci 00.0 on end # x4 M.2/M (J_SSD1)
register "PcieRpEnable[8]" = "1"
@@ -130,16 +111,6 @@ chip soc/intel/skylake
register "PcieRpLtrEnable[8]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
end
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1e.0 off end # UART 0
- device pci 1e.1 off end # UART 1
- device pci 1e.2 off end # GSPI 0
- device pci 1e.3 off end # GSPI 1
- device pci 1e.4 off end # eMMC
- device pci 1e.5 off end # SDIO
- device pci 1e.6 off end # SDXC
device pci 1f.0 on # LPC Interface
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"
@@ -159,7 +130,5 @@ chip soc/intel/skylake
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
- device pci 1f.7 off end # Trace Hub
end
end