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-rw-r--r--src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb108
1 files changed, 54 insertions, 54 deletions
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
index 96d52a4822..b7745a3d74 100644
--- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
+++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
@@ -64,16 +64,16 @@ chip soc/intel/cannonlake
device domain 0 on
subsystemid 0x1558 0x1401 inherit
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 on # SA Thermal device
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 on # SA Thermal device
register "Device4Enable" = "1"
end
- device pci 12.0 on end # Thermal Subsystem
- device pci 12.5 off end # UFS SCS
- device pci 12.6 off end # GSPI #2
- device pci 13.0 off end # Integrated Sensor Hub
- device pci 14.0 on # USB xHCI
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 12.5 off end # UFS SCS
+ device pci 12.6 off end # GSPI #2
+ device pci 13.0 off end # Integrated Sensor Hub
+ device pci 14.0 on # USB xHCI
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2
@@ -85,15 +85,15 @@ chip soc/intel/cannonlake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3
end
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.3 on
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.3 on # CNVi wifi
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
- end # CNVi wifi
- device pci 14.5 off end # SDCard
- device pci 15.0 on # I2C #0
+ end
+ device pci 14.5 off end # SDCard
+ device pci 15.0 on # I2C #0
chip drivers/i2c/hid
register "generic.hid" = ""ELAN040D""
register "generic.desc" = ""ELAN Touchpad""
@@ -103,16 +103,16 @@ chip soc/intel/cannonlake
device i2c 15 on end
end
end
- device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 16.5 off end # Management Engine Interface 4
- device pci 17.0 on # SATA
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on # SATA
register "SataMode" = "Sata_AHCI"
register "SataSalpSupport" = "1"
# Port 2 (J_SSD2)
@@ -122,24 +122,24 @@ chip soc/intel/cannonlake
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1"
end
- device pci 19.0 off end # I2C #4
- device pci 19.1 off end # I2C #5
- device pci 19.2 on end # UART #2
- device pci 1a.0 off end # eMMC
- device pci 1c.0 off end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 off end # PCI Express Port 5
- device pci 1c.5 on # PCI Express Port 6
+ device pci 19.0 off end # I2C #4
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 on end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1c.0 off end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 on # PCI Express Port 6
device pci 00.0 on end # x1 Card reader
register "PcieRpEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[3]" = "5"
register "PcieClkSrcClkReq[3]" = "3"
end
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 on # PCI Express Port 8
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 on # PCI Express Port 8
chip drivers/wifi/generic
device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
end
@@ -150,7 +150,7 @@ chip soc/intel/cannonlake
register "PcieRpSlotImplemented[7]" = "1"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
end
- device pci 1d.0 on # PCI Express Port 9
+ device pci 1d.0 on # PCI Express Port 9
device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
@@ -159,10 +159,10 @@ chip soc/intel/cannonlake
register "PcieRpSlotImplemented[8]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
end
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 on # PCI Express Port 13
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 on # PCI Express Port 13
device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
@@ -171,14 +171,14 @@ chip soc/intel/cannonlake
register "PcieRpSlotImplemented[12]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
end
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1e.0 off end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on # LPC Interface
+ device pci 1d.5 off end # PCI Express Port 14
+ device pci 1d.6 off end # PCI Express Port 15
+ device pci 1d.7 off end # PCI Express Port 16
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on # LPC Interface
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
register "gen1_dec" = "0x000c0081"
@@ -192,13 +192,13 @@ chip soc/intel/cannonlake
device pnp 0c31.0 on end
end
end
- device pci 1f.1 hidden end # P2SB
- device pci 1f.2 hidden end # Power Management Controller
- device pci 1f.3 on # Intel HDA
+ device pci 1f.1 hidden end # P2SB
+ device pci 1f.2 hidden end # Power Management Controller
+ device pci 1f.3 on # Intel HDA
register "PchHdaAudioLinkHda" = "1"
end
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
end
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 15:23:30 +0000