1 files changed, 46 insertions, 0 deletions
diff --git a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c
new file mode 100644
index 0000000000..36332cc6e3
--- /dev/null
+++ b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/soc.h>
+#include <soc/spi.h>
+#include <soc/uart.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+		if (!uart_is_enabled(0))
+			uart_setup(0, CONFIG_TTYS0_BAUD);
+		if (!uart_is_enabled(1))
+			uart_setup(0, CONFIG_TTYS0_BAUD);
+	}
+}
+
+static void configure_spi_flash(void)
+{
+	/* FIXME: Only tested on EM100 Pro */
+	spi_init_custom(0, // bus
+			25000000, // speed Hz
+			0, // idle low disabled
+			0, // zero idle cycles between transfers
+			0, // MSB first
+			0, // Chip select 0
+			1); // assert is high
+}
+
+void bootblock_mainboard_init(void)
+{
+	configure_spi_flash();
+}