diff options
Diffstat (limited to 'src/mainboard/bap/ode_e21XX/romstage.c')
| -rw-r--r-- | src/mainboard/bap/ode_e21XX/romstage.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index a5c529e7c5..8466e251db 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -32,6 +32,10 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81866d/f81866d.h> + +#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -54,7 +58,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); - + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); post_code(0x31); console_init(); } @@ -68,16 +72,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); - /* - * This refers to LpcClkDrvSth settling time. Without this setting, processor - * initialization is slow or incorrect, so this wait has been replicated from - * earlier development boards. - */ - { - int i; - for(i = 0; i < 200000; i++) inb(0xCD6); - } - post_code(0x37); AGESAWRAPPER(amdinitreset); |