diff options
Diffstat (limited to 'src/mainboard/bap/ode_e20XX/romstage.c')
-rw-r--r-- | src/mainboard/bap/ode_e20XX/romstage.c | 89 |
1 files changed, 8 insertions, 81 deletions
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index cf92d0cb96..9921f368f4 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -15,37 +15,21 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> + +#include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81866d/f81866d.h> -#include "cbmem.h" + #define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + outb(0xea, 0xcd6); + outb(0x1, 0xcd7); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -53,62 +37,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for(i = 0; i < 200000; i++) - val = inb(0xcd6); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); } |