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-rw-r--r--src/mainboard/asus/a8n_e/romstage.c2
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/romstage.c10
-rw-r--r--src/mainboard/asus/a8v-e_se/romstage.c10
-rw-r--r--src/mainboard/asus/k8v-x/romstage.c10
-rw-r--r--src/mainboard/asus/m2n-e/romstage.c2
-rw-r--r--src/mainboard/asus/m2v-mx_se/romstage.c14
-rw-r--r--src/mainboard/asus/m2v/romstage.c10
-rw-r--r--src/mainboard/asus/m4a78-em/romstage.c2
-rw-r--r--src/mainboard/asus/m4a785-m/romstage.c2
-rw-r--r--src/mainboard/asus/m5a88-v/romstage.c2
10 files changed, 32 insertions, 32 deletions
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index c5d3f073f3..a0ce8460cf 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -128,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index e642cbd1a8..6e099b32db 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -65,7 +65,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset\n");
+ printk(BIOS_DEBUG, "soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
enable_rom_decode();
- print_info("now booting... romstage\n");
+ printk(BIOS_INFO, "now booting... romstage\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) {
@@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
}
- print_info("now booting... real_main\n");
+ printk(BIOS_INFO, "now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
- print_info("now booting... Core0 started\n");
+ printk(BIOS_INFO, "now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
@@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= k8t890_early_setup_ht();
if (needs_reset) {
- print_debug("ht reset -\n");
+ printk(BIOS_DEBUG, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index ebdb095a43..61e27d0095 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -65,7 +65,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset\n");
+ printk(BIOS_DEBUG, "soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
enable_rom_decode();
- print_info("now booting... fallback\n");
+ printk(BIOS_INFO, "now booting... fallback\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) {
@@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
}
- print_info("now booting... real_main\n");
+ printk(BIOS_INFO, "now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
- print_info("now booting... Core0 started\n");
+ printk(BIOS_INFO, "now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
@@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= k8t890_early_setup_ht();
if (needs_reset) {
- print_debug("ht reset -\n");
+ printk(BIOS_DEBUG, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 51276188e8..048da22fce 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -63,7 +63,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset\n");
+ printk(BIOS_DEBUG, "soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
enable_rom_decode();
- print_info("now booting... fallback\n");
+ printk(BIOS_INFO, "now booting... fallback\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) {
@@ -120,7 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
}
- print_info("now booting... real_main\n");
+ printk(BIOS_INFO, "now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
- print_info("now booting... Core0 started\n");
+ printk(BIOS_INFO, "now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= k8t890_early_setup_ht();
if (needs_reset) {
- print_debug("ht reset -\n");
+ printk(BIOS_DEBUG, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index 4cf64cc571..aba3758a05 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
* effective too.
*/
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 0b1555c2e4..93b9202045 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -70,7 +70,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void ldtstop_sb(void)
{
- print_debug("toggle LDTSTP#\n");
+ printk(BIOS_DEBUG, "toggle LDTSTP#\n");
/* fix errata #181, disable DRAM controller it will get enabled later */
u8 tmp = pci_read_config8(PCI_DEV(0, 0x18, 2), 0x94);
@@ -81,7 +81,7 @@ static void ldtstop_sb(void)
reg = reg ^ (1 << 0);
outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
- print_debug("done\n");
+ printk(BIOS_DEBUG, "done\n");
}
#include "cpu/amd/model_fxx/fidvid.c"
@@ -92,7 +92,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset\n");
+ printk(BIOS_DEBUG, "soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -154,11 +154,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
needs_reset = optimize_link_coherent_ht();
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
needs_reset |= optimize_link_incoherent_ht(sysinfo);
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
needs_reset |= k8t890_early_setup_ht();
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
vt8237_early_network_init(NULL);
vt8237_early_spi_init();
@@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
vt8237_sb_enable_fid_vid();
enable_fid_change();
- print_debug("after enable_fid_change\n");
+ printk(BIOS_DEBUG, "after enable_fid_change\n");
init_fidvid_bsp(bsp_apicid);
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 4040c60800..bfc3db0b6c 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -76,7 +76,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset\n");
+ printk(BIOS_DEBUG, "soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -254,11 +254,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
needs_reset = optimize_link_coherent_ht();
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
needs_reset |= optimize_link_incoherent_ht(sysinfo);
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
needs_reset |= k8t890_early_setup_ht();
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
if (needs_reset) {
printk(BIOS_DEBUG, "ht reset -\n");
@@ -271,7 +271,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
vt8237_sb_enable_fid_vid();
enable_fid_change();
- print_debug("after enable_fid_change\n");
+ printk(BIOS_DEBUG, "after enable_fid_change\n");
init_fidvid_bsp(bsp_apicid);
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 01df5c8cbe..7c93767e17 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 9b14cd355a..328955a0d7 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 3bf8e80f36..baa38acbb6 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 20:55:06 +0000