diff options
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r-- | src/mainboard/asus/m2n-e/romstage.c | 4 | ||||
-rw-r--r-- | src/mainboard/asus/m4a78-em/romstage.c | 6 | ||||
-rw-r--r-- | src/mainboard/asus/m4a785-m/romstage.c | 6 |
3 files changed, 0 insertions, 16 deletions
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index eaa9edaace..66a2b9ff1c 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -123,10 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_mb_resource_map(); uart_init(); report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 56204fb230..68caa0120b 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8712f_kill_watchdog(); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 56204fb230..68caa0120b 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8712f_kill_watchdog(); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |