diff options
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/p3b-f/romstage.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 0867886fa0..cde5400ff4 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -29,6 +29,7 @@ #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb_early_pm.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" @@ -49,6 +50,37 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" +/* + * ASUS P3B-F specific SPD enable magic. + * + * Setting the byte at offset 0x37 in the PM I/O space to 0x6f will make the + * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD + * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which + * will make RAM init fail. + * + * Tested values for PM I/O offset 0x37: + * 0x67: 11 00 111: Only SMBus/I2C offsets 0x48/0x49/0x2d accessible + * 0x6f: 11 01 111: Only SMBus/I2C offsets 0x50-0x53 (SPD) accessible + * 0x77: 11 10 111: Only SMBus/I2C offset 0x69 accessible + * + * PM I/O space offset 0x37 is GPOREG[31:24], i.e. it controls the GPIOs + * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28 + * control which SMBus/I2C offsets can be accessed. + */ +static void enable_spd(void) +{ + outb(0x6f, PM_IO_BASE + 0x37); +} + +/* + * Disable SPD access after RAM init to allow access to SMBus/I2C offsets + * 0x48/0x49/0x2d, which is required e.g. by lm-sensors. + */ +static void disable_spd(void) +{ + outb(0x67, PM_IO_BASE + 0x37); +} + static void main(unsigned long bist) { if (bist == 0) @@ -64,10 +96,16 @@ static void main(unsigned long bist) i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ enable_smbus(); + enable_pm(); + + enable_spd(); + /* dump_spd_registers(); */ sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); /* ram_check(0, 640 * 1024); */ + + disable_spd(); } |