diff options
Diffstat (limited to 'src/mainboard/asus')
37 files changed, 903 insertions, 903 deletions
diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb index 065a7ab7cb..72380d9e8a 100644 --- a/src/mainboard/asus/a8n_e/Config.lb +++ b/src/mainboard/asus/a8n_e/Config.lb @@ -21,36 +21,36 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end driver mainboard.o # Needed by irq_tables and mptable and acpi_tables. object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -60,8 +60,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -69,7 +69,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -81,24 +81,24 @@ end mainboardinit southbridge/nvidia/ck804/id.inc ldscript /southbridge/nvidia/ck804/id.lds # ROMSTRAP table for CK804. -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end end mainboardinit cpu/amd/car/cache_as_ram.inc -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb index 5f4c65715e..4682869577 100644 --- a/src/mainboard/asus/a8n_e/Options.lb +++ b/src/mainboard/asus/a8n_e/Options.lb @@ -19,153 +19,153 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_MEM_TRAIN_SEQ +uses CONFIG_WAIT_BEFORE_CPUS_INIT +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK uses CONFIG_USE_PRINTK_IN_CAR -default ROM_SIZE = 512 * 1024 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 252 * 1024 -default FAILOVER_SIZE = 4 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_FAILOVER_BOOT = 1 -default HAVE_HARD_RESET = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 13 -default HAVE_MP_TABLE = 1 -default HAVE_OPTION_TABLE = 1 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 252 * 1024 +default CONFIG_FAILOVER_SIZE = 4 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FAILOVER_BOOT = 1 +default CONFIG_HAVE_HARD_RESET = 1 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 13 +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_OPTION_TABLE = 1 # Move the default coreboot CMOS range off of AMD RTC registers. -default LB_CKS_RANGE_START = 49 -default LB_CKS_RANGE_END = 122 -default LB_CKS_LOC = 123 +default CONFIG_LB_CKS_RANGE_START = 49 +default CONFIG_LB_CKS_RANGE_END = 122 +default CONFIG_LB_CKS_LOC = 123 # SMP support (only worry about 2 micro processors). default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 # 1G memory hole. -default HW_MEM_HOLE_SIZEK = 0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 # HT Unit ID offset, default is 1, the typical one. -default HT_CHAIN_UNITID_BASE = 0 +default CONFIG_HT_CHAIN_UNITID_BASE = 0 # Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default HT_CHAIN_END_UNITID_BASE = 0x10 +# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x10 # Make the SB HT chain on bus 0, default is not (0). -default SB_HT_CHAIN_ON_BUS0 = 2 +default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2 # Only offset for SB chain?, default is yes(1). -default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 # default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console default CONFIG_CONSOLE_VGA = 1 # For VGA console default CONFIG_PCI_ROM_RUN = 1 # For VGA console -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xc8000 -default DCACHE_RAM_SIZE = 32 * 1024 -default DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xc8000 +default CONFIG_DCACHE_RAM_SIZE = 32 * 1024 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 default CONFIG_USE_INIT = 0 default CONFIG_AP_CODE_IN_CAR = 0 -default MEM_TRAIN_SEQ = 2 -default WAIT_BEFORE_CPUS_INIT = 0 -# default ENABLE_APIC_EXT_ID = 0 -# default APIC_ID_OFFSET = 0x10 -# default LIFT_BSP_APIC_ID = 0 +default CONFIG_MEM_TRAIN_SEQ = 2 +default CONFIG_WAIT_BEFORE_CPUS_INIT = 0 +# default CONFIG_ENABLE_APIC_EXT_ID = 0 +# default CONFIG_APIC_ID_OFFSET = 0x10 +# default CONFIG_LIFT_BSP_APIC_ID = 0 # default CONFIG_PCI_64BIT_PREF_MEM = 1 default CONFIG_IOAPIC = 1 -default MAINBOARD_PART_NUMBER = "A8N-E" -default MAINBOARD_VENDOR = "ASUS" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 +default CONFIG_MAINBOARD_PART_NUMBER = "A8N-E" +default CONFIG_MAINBOARD_VENDOR = "ASUS" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 # Only use the option table in a normal image. -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE) -default _RAMBASE = 0x00004000 +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE) +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_GDB_STUB = 0 default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 -default DEFAULT_CONSOLE_LOGLEVEL = 8 -default MAXIMUM_CONSOLE_LOGLEVEL = 8 -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # # CBFS diff --git a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c index 1e02e6e0be..a45d8d7966 100644 --- a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c +++ b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c @@ -50,7 +50,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 /* Used by ck894_early_setup(). */ #define CK804_NUM 1 @@ -99,10 +99,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) \ - || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \ + || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -166,7 +166,7 @@ normal_image: fallback_image: -#if HAVE_FAILOVER_BOOT == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ @@ -175,27 +175,27 @@ fallback_image: ; } -#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) ... */ +#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT == 1 -#if USE_FAILOVER_IMAGE == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 +#if CONFIG_USE_FAILOVER_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -215,7 +215,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); it8712f_24mhz_clkin(); - it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -266,4 +266,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb index a53b262d16..242c104eac 100644 --- a/src/mainboard/asus/a8v-e_se/Config.lb +++ b/src/mainboard/asus/a8v-e_se/Config.lb @@ -20,42 +20,42 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 arch i386 end driver mainboard.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/dsdt.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds mainboardinit southbridge/via/k8t890/romstrap.inc @@ -71,7 +71,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/amd/car/cache_as_ram.lds end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -81,7 +81,7 @@ end mainboardinit cpu/amd/car/cache_as_ram.inc -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb index a471b418b2..75c404dd92 100644 --- a/src/mainboard/asus/a8v-e_se/Options.lb +++ b/src/mainboard/asus/a8v-e_se/Options.lb @@ -17,156 +17,156 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -# uses USE_OPTION_TABLE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +# uses CONFIG_USE_OPTION_TABLE # uses CONFIG_LB_MEM_TOPK -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN # bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE # bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY # bx_b005+ -uses SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_USE_PRINTK_IN_CAR -default ROM_SIZE = 512 * 1024 -default FALLBACK_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 11 # FIXME? -default HAVE_MP_TABLE = 1 -default HAVE_OPTION_TABLE = 0 # FIXME +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_FALLBACK_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 0 +default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME? +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME # Move the default coreboot CMOS range off of AMD RTC registers. -default LB_CKS_RANGE_START = 49 -default LB_CKS_RANGE_END = 122 -default LB_CKS_LOC = 123 +default CONFIG_LB_CKS_RANGE_START = 49 +default CONFIG_LB_CKS_RANGE_END = 122 +default CONFIG_LB_CKS_LOC = 123 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 -default HAVE_ACPI_TABLES = 1 +default CONFIG_HAVE_ACPI_TABLES = 1 # 1G memory hole # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 # Opteron K8 1G HT support -default K8_HT_FREQ_1G_SUPPORT = 1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 # HT Unit ID offset, default is 1, the typical one. -default HT_CHAIN_UNITID_BASE = 0x0 +default CONFIG_HT_CHAIN_UNITID_BASE = 0x0 # Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default HT_CHAIN_END_UNITID_BASE = 0x0 +# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 # Make the SB HT chain on bus 0, default is not (0). # bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2 # bx_b005+ make the SB HT chain on bus 0. -default SB_HT_CHAIN_ON_BUS0 = 1 +default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1 # Only offset for SB chain?, default is yes(1). -default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA. -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xcc000 -default DCACHE_RAM_SIZE = 0x4000 -default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xcc000 +default CONFIG_DCACHE_RAM_SIZE = 0x4000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 default CONFIG_USE_INIT = 0 -default ENABLE_APIC_EXT_ID = 0 -default APIC_ID_OFFSET = 0x10 -default LIFT_BSP_APIC_ID = 0 +default CONFIG_ENABLE_APIC_EXT_ID = 0 +default CONFIG_APIC_ID_OFFSET = 0x10 +default CONFIG_LIFT_BSP_APIC_ID = 0 default CONFIG_IOAPIC = 1 -default MAINBOARD_VENDOR = "ASUS" -default MAINBOARD_PART_NUMBER = "A8V-E SE" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default ROM_IMAGE_SIZE = 64 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "ASUS" +default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 +# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. # default CONFIG_LB_MEM_TOPK = 2048 -default _RAMBASE = 0x00004000 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_RAMBASE = 0x00004000 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_GDB_STUB = 0 default CONFIG_USE_PRINTK_IN_CAR = 1 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 8 -default MAXIMUM_CONSOLE_LOGLEVEL = 8 -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # # CBFS # diff --git a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c index 0a8ca60a8b..b76d011910 100644 --- a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c +++ b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c @@ -178,7 +178,7 @@ void sio_init(void) pnp_exit_ext_func_mode(GPIO_DEV); } -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -187,7 +187,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) unsigned last_boot_normal_x = 1; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); enable_rom_decode(); @@ -232,7 +232,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -251,11 +251,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = - (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/m2v-mx_se/Config.lb b/src/mainboard/asus/m2v-mx_se/Config.lb index 76935320f0..c7f7d6e51a 100644 --- a/src/mainboard/asus/m2v-mx_se/Config.lb +++ b/src/mainboard/asus/m2v-mx_se/Config.lb @@ -20,18 +20,18 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/dsdt.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -39,19 +39,19 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds mainboardinit southbridge/via/k8t890/romstrap.inc @@ -67,7 +67,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/amd/car/cache_as_ram.lds end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ end mainboardinit cpu/amd/car/cache_as_ram.inc -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb index 8f388d5219..d1a08e2c7f 100644 --- a/src/mainboard/asus/m2v-mx_se/Options.lb +++ b/src/mainboard/asus/m2v-mx_se/Options.lb @@ -17,159 +17,159 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -# uses USE_OPTION_TABLE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +# uses CONFIG_USE_OPTION_TABLE uses CONFIG_LB_MEM_TOPK -uses HAVE_ACPI_TABLES -uses HAVE_MAINBOARD_RESOURCES -uses HAVE_ACPI_RESUME -uses HAVE_LOW_TABLES -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_MAINBOARD_RESOURCES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_LOW_TABLES +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN # bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE # bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY # bx_b005+ -uses SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_USE_PRINTK_IN_CAR -default HAVE_FALLBACK_BOOT = 1 -default HAVE_HARD_RESET = 1 -default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 11 # FIXME? -default HAVE_MP_TABLE = 0 -default HAVE_OPTION_TABLE = 0 # FIXME +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_HARD_RESET = 1 +default CONFIG_HAVE_PIRQ_TABLE = 0 +default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME? +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME # Move the default coreboot CMOS range off of AMD RTC registers. -default LB_CKS_RANGE_START = 49 -default LB_CKS_RANGE_END = 122 -default LB_CKS_LOC = 123 +default CONFIG_LB_CKS_RANGE_START = 49 +default CONFIG_LB_CKS_RANGE_END = 122 +default CONFIG_LB_CKS_LOC = 123 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 -default HAVE_ACPI_TABLES = 1 -default HAVE_MAINBOARD_RESOURCES = 1 -default HAVE_LOW_TABLES = 0 -default HAVE_ACPI_RESUME = 1 +default CONFIG_HAVE_ACPI_TABLES = 1 +default CONFIG_HAVE_MAINBOARD_RESOURCES = 1 +default CONFIG_HAVE_LOW_TABLES = 0 +default CONFIG_HAVE_ACPI_RESUME = 1 # 1G memory hole # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 # Opteron K8 1G HT support -default K8_HT_FREQ_1G_SUPPORT = 1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 # HT Unit ID offset, default is 1, the typical one. -default HT_CHAIN_UNITID_BASE = 0x0 +default CONFIG_HT_CHAIN_UNITID_BASE = 0x0 # Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default HT_CHAIN_END_UNITID_BASE = 0x0 +# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 # Make the SB HT chain on bus 0, default is not (0). # bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2 # bx_b005+ make the SB HT chain on bus 0. -default SB_HT_CHAIN_ON_BUS0 = 1 +default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1 # Only offset for SB chain?, default is yes(1). -default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. default CONFIG_PCI_ROM_RUN = 0 # Needed for VGA. -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xcc000 -default DCACHE_RAM_SIZE = 0x4000 -default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xcc000 +default CONFIG_DCACHE_RAM_SIZE = 0x4000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 default CONFIG_USE_INIT = 0 -default ENABLE_APIC_EXT_ID = 0 -default APIC_ID_OFFSET = 0x10 -default LIFT_BSP_APIC_ID = 0 +default CONFIG_ENABLE_APIC_EXT_ID = 0 +default CONFIG_APIC_ID_OFFSET = 0x10 +default CONFIG_LIFT_BSP_APIC_ID = 0 default CONFIG_IOAPIC = 1 -default MAINBOARD_VENDOR = "ASUS" -default MAINBOARD_PART_NUMBER = "M2V-MX SE" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "ASUS" +default CONFIG_MAINBOARD_PART_NUMBER = "M2V-MX SE" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 +# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. default CONFIG_LB_MEM_TOPK = 32768 # to 1MB -default _RAMBASE = 0x1F00000 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_RAMBASE = 0x1F00000 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_GDB_STUB = 0 default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # # CBFS # diff --git a/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c b/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c index 15dcda5ec1..e5d18e1c94 100644 --- a/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c +++ b/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); /* If we want to wait for core1 done before DQS training, set it to 0. */ #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -183,12 +183,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = - (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p; u8 reg; sio_init(); - it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); it8712f_enable_3vsbsw(); uart_init(); diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c index f6bf656e50..c68fe6174b 100644 --- a/src/mainboard/asus/m2v-mx_se/mainboard.c +++ b/src/mainboard/asus/m2v-mx_se/mainboard.c @@ -25,11 +25,11 @@ int add_mainboard_resources(struct lb_memory *mem) { -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 lb_add_memory_range(mem, LB_MEM_RESERVED, - _RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - _RAMBASE)); + CONFIG_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_RAMBASE)); lb_add_memory_range(mem, LB_MEM_RESERVED, - DCACHE_RAM_BASE, DCACHE_RAM_SIZE); + CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); #endif return 0; } diff --git a/src/mainboard/asus/mew-am/Config.lb b/src/mainboard/asus/mew-am/Config.lb index 76ddff64a8..c6486831df 100644 --- a/src/mainboard/asus/mew-am/Config.lb +++ b/src/mainboard/asus/mew-am/Config.lb @@ -18,40 +18,40 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -61,7 +61,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/mew-am/Options.lb b/src/mainboard/asus/mew-am/Options.lb index 95be45a13d..c0837b2dda 100644 --- a/src/mainboard/asus/mew-am/Options.lb +++ b/src/mainboard/asus/mew-am/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 512 * 1024 # Override this in targets/*/Config.lb. -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 512 * 1024 # Override this in targets/*/Config.lb. +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. -default MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb. default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. diff --git a/src/mainboard/asus/mew-am/auto.c b/src/mainboard/asus/mew-am/auto.c index ea09d6c371..05a163d779 100644 --- a/src/mainboard/asus/mew-am/auto.c +++ b/src/mainboard/asus/mew-am/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/mew-am/irq_tables.c b/src/mainboard/asus/mew-am/irq_tables.c index 84d738dd2d..e07ee20b96 100644 --- a/src/mainboard/asus/mew-am/irq_tables.c +++ b/src/mainboard/asus/mew-am/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x1f << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb index 44439707dd..60f4e152b6 100644 --- a/src/mainboard/asus/mew-vm/Config.lb +++ b/src/mainboard/asus/mew-vm/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/mew-vm/Options.lb b/src/mainboard/asus/mew-vm/Options.lb index fa0eedc074..71f854d127 100644 --- a/src/mainboard/asus/mew-vm/Options.lb +++ b/src/mainboard/asus/mew-vm/Options.lb @@ -1,50 +1,50 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_IDE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 512*1024 ### ### Build options @@ -53,28 +53,28 @@ default ROM_SIZE = 512*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 ## ## no MP table ## -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_MP_TABLE = 0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET = 0 +default CONFIG_HAVE_HARD_RESET = 0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 11 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 11 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 ## IDE Support default CONFIG_IDE = 1 @@ -83,36 +83,36 @@ default CONFIG_IDE = 1 ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -122,21 +122,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -148,13 +148,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 default CONFIG_UDELAY_TSC=1 diff --git a/src/mainboard/asus/mew-vm/auto.c b/src/mainboard/asus/mew-vm/auto.c index 721f6116b1..f53083f2a5 100644 --- a/src/mainboard/asus/mew-vm/auto.c +++ b/src/mainboard/asus/mew-vm/auto.c @@ -58,7 +58,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE); + lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/asus/p2b-d/Config.lb b/src/mainboard/asus/p2b-d/Config.lb index cb886bf914..a0486cd209 100644 --- a/src/mainboard/asus/p2b-d/Config.lb +++ b/src/mainboard/asus/p2b-d/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b-d/Options.lb b/src/mainboard/asus/p2b-d/Options.lb index 946cc8a017..2409c14956 100644 --- a/src/mainboard/asus/p2b-d/Options.lb +++ b/src/mainboard/asus/p2b-d/Options.lb @@ -18,89 +18,89 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_SMP uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 1 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_IOAPIC = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 default CONFIG_CBFS = 0 diff --git a/src/mainboard/asus/p2b-d/auto.c b/src/mainboard/asus/p2b-d/auto.c index f25e34e578..747ba77b35 100644 --- a/src/mainboard/asus/p2b-d/auto.c +++ b/src/mainboard/asus/p2b-d/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) enable_lapic(); /* FIXME? */ } - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-d/irq_tables.c b/src/mainboard/asus/p2b-d/irq_tables.c index e8c6ff197d..05a465cc94 100644 --- a/src/mainboard/asus/p2b-d/irq_tables.c +++ b/src/mainboard/asus/p2b-d/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p2b-ds/Config.lb b/src/mainboard/asus/p2b-ds/Config.lb index 8d83be9ef1..2b6599458a 100644 --- a/src/mainboard/asus/p2b-ds/Config.lb +++ b/src/mainboard/asus/p2b-ds/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b-ds/Options.lb b/src/mainboard/asus/p2b-ds/Options.lb index f907eac3d8..c069939fc5 100644 --- a/src/mainboard/asus/p2b-ds/Options.lb +++ b/src/mainboard/asus/p2b-ds/Options.lb @@ -18,89 +18,89 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_SMP uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 1 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_IOAPIC = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p2b-ds/auto.c b/src/mainboard/asus/p2b-ds/auto.c index 95cfa64765..aaa7ae94e6 100644 --- a/src/mainboard/asus/p2b-ds/auto.c +++ b/src/mainboard/asus/p2b-ds/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) enable_lapic(); /* FIXME? */ } - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b-ds/irq_tables.c index bc3a64741c..29b6f54885 100644 --- a/src/mainboard/asus/p2b-ds/irq_tables.c +++ b/src/mainboard/asus/p2b-ds/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p2b-f/Config.lb b/src/mainboard/asus/p2b-f/Config.lb index 5bef9da403..f6995beedf 100644 --- a/src/mainboard/asus/p2b-f/Config.lb +++ b/src/mainboard/asus/p2b-f/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b-f/Options.lb b/src/mainboard/asus/p2b-f/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/asus/p2b-f/Options.lb +++ b/src/mainboard/asus/p2b-f/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p2b-f/auto.c b/src/mainboard/asus/p2b-f/auto.c index 0c81b7f0d0..191c9ffd4c 100644 --- a/src/mainboard/asus/p2b-f/auto.c +++ b/src/mainboard/asus/p2b-f/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-f/irq_tables.c b/src/mainboard/asus/p2b-f/irq_tables.c index bbdf7bd9ae..f33c8cab55 100644 --- a/src/mainboard/asus/p2b-f/irq_tables.c +++ b/src/mainboard/asus/p2b-f/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p2b/Config.lb b/src/mainboard/asus/p2b/Config.lb index 2b54440f30..ef04497653 100644 --- a/src/mainboard/asus/p2b/Config.lb +++ b/src/mainboard/asus/p2b/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b/Options.lb b/src/mainboard/asus/p2b/Options.lb index e6bd850cbd..db9fcecb29 100644 --- a/src/mainboard/asus/p2b/Options.lb +++ b/src/mainboard/asus/p2b/Options.lb @@ -18,83 +18,83 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p2b/auto.c b/src/mainboard/asus/p2b/auto.c index 2e60b1c526..1b5891e519 100644 --- a/src/mainboard/asus/p2b/auto.c +++ b/src/mainboard/asus/p2b/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b/irq_tables.c b/src/mainboard/asus/p2b/irq_tables.c index f957dc878d..e0daa56076 100644 --- a/src/mainboard/asus/p2b/irq_tables.c +++ b/src/mainboard/asus/p2b/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p3b-f/Config.lb b/src/mainboard/asus/p3b-f/Config.lb index 1b752437c4..67b4b39627 100644 --- a/src/mainboard/asus/p3b-f/Config.lb +++ b/src/mainboard/asus/p3b-f/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p3b-f/Options.lb b/src/mainboard/asus/p3b-f/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/asus/p3b-f/Options.lb +++ b/src/mainboard/asus/p3b-f/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p3b-f/auto.c b/src/mainboard/asus/p3b-f/auto.c index b4880d556b..e300bf6794 100644 --- a/src/mainboard/asus/p3b-f/auto.c +++ b/src/mainboard/asus/p3b-f/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p3b-f/irq_tables.c b/src/mainboard/asus/p3b-f/irq_tables.c index 47ef7f2f70..2cc0565431 100644 --- a/src/mainboard/asus/p3b-f/irq_tables.c +++ b/src/mainboard/asus/p3b-f/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ |