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-rw-r--r--src/mainboard/asus/p5gc-mx/devicetree.cb4
-rw-r--r--src/mainboard/asus/p5qpl-am/devicetree.cb2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb
index ad9b961dca..a9cad93e33 100644
--- a/src/mainboard/asus/p5gc-mx/devicetree.cb
+++ b/src/mainboard/asus/p5gc-mx/devicetree.cb
@@ -38,8 +38,8 @@ chip northbridge/intel/i945
register "gpe0_en" = "0"
- register "ide_enable_primary" = "0x1"
- register "ide_enable_secondary" = "0x0"
+ register "ide_enable_primary" = "true"
+ register "ide_enable_secondary" = "false"
register "p_cnt_throttling_supported" = "0"
diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb
index 82b1c61078..104485116e 100644
--- a/src/mainboard/asus/p5qpl-am/devicetree.cb
+++ b/src/mainboard/asus/p5qpl-am/devicetree.cb
@@ -29,7 +29,7 @@ chip northbridge/intel/x4x # Northbridge
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
- register "ide_enable_primary" = "0x1"
+ register "ide_enable_primary" = "true"
register "gpe0_en" = "0x04000440"
register "gen1_dec" = "0x00000295" # HWM