summaryrefslogtreecommitdiff
path: root/src/mainboard/asus/p5qc/dsdt.asl
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/asus/p5qc/dsdt.asl')
-rw-r--r--src/mainboard/asus/p5qc/dsdt.asl43
1 files changed, 43 insertions, 0 deletions
diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl
new file mode 100644
index 0000000000..4888b9ce13
--- /dev/null
+++ b/src/mainboard/asus/p5qc/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/i82801jx/i82801jx.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x00000001 // OEM revision
+)
+{
+ // global NVS and variables
+ #include "acpi/platform.asl"
+ #include <southbridge/intel/i82801jx/acpi/globalnvs.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/x4x/acpi/x4x.asl>
+ #include <southbridge/intel/i82801jx/acpi/ich10.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801jx/acpi/sleepstates.asl>
+}