diff options
Diffstat (limited to 'src/mainboard/asus/p2b')
| -rw-r--r-- | src/mainboard/asus/p2b/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/asus/p2b/acpi_tables.c | 28 | ||||
| -rw-r--r-- | src/mainboard/asus/p2b/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/asus/p2b/dsdt.asl | 101 |
4 files changed, 133 insertions, 0 deletions
diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index cb1c8507e3..77f2d2546e 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/asus/p2b/acpi_tables.c b/src/mainboard/asus/p2b/acpi_tables.c new file mode 100644 index 0000000000..6ed25d9d1d --- /dev/null +++ b/src/mainboard/asus/p2b/acpi_tables.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* mainboard has no ioapic */ + return current; +} diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index a193e9ead2..f4bfbad87c 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -54,6 +54,9 @@ chip northbridge/intel/i440bx # Northbridge register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" register "ide1_drive1_udma33_enable" = "0" + register "thrm_polarity" = "1" + register "lid_polarity" = "1" + register "gpo" = "0x7fffbbff" end end end diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl new file mode 100644 index 0000000000..15c39d2116 --- /dev/null +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) +{ + /* Define the main processor.*/ + Scope (\_PR) + { + /* Looks like the P_CNT field can't be a method or name + * and has to be hardcoded to 0xe410 or generated in SSDT */ + Processor (CPU0, 0x01, 0xe410, 0x06) {} + } + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + + /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */ + /* + 000b / 0x0: soft off/suspend to disk (soff/std) s5 + 001b / 0x1: suspend to ram (str) s3 + 010b / 0x2: powered on suspend, context lost (poscl) s1 + 011b / 0x3: powered on suspend, cpu context lost (posccl) s2 + 100b / 0x4: powered on suspend, context maintained (pos) s4 + 101b / 0x5: working (clock control) s0 + 110b / 0x6: reserved + 111b / 0x7: reserved + */ + Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) + Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) + Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0, LNKA, 0 }, + Package (0x04) { 0x0001FFFF, 1, LNKB, 0 }, + Package (0x04) { 0x0001FFFF, 2, LNKC, 0 }, + Package (0x04) { 0x0001FFFF, 3, LNKD, 0 }, + + Package (0x04) { 0x0004FFFF, 0, LNKA, 0 }, + Package (0x04) { 0x0004FFFF, 1, LNKB, 0 }, + Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, + Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, + + Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, + Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, + Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, + Package (0x04) { 0x0009FFFF, 3, LNKC, 0 }, + + Package (0x04) { 0x000AFFFF, 0, LNKC, 0 }, + Package (0x04) { 0x000AFFFF, 1, LNKD, 0 }, + Package (0x04) { 0x000AFFFF, 2, LNKA, 0 }, + Package (0x04) { 0x000AFFFF, 3, LNKB, 0 }, + + Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, + Package (0x04) { 0x000BFFFF, 1, LNKC, 0 }, + Package (0x04) { 0x000BFFFF, 2, LNKD, 0 }, + Package (0x04) { 0x000BFFFF, 3, LNKA, 0 }, + + Package (0x04) { 0x000CFFFF, 0, LNKA, 0 }, + Package (0x04) { 0x000CFFFF, 1, LNKB, 0 }, + Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, + Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, + + }) + +#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl" +#include "southbridge/intel/i82371eb/acpi/isabridge.asl" + } +#include "southbridge/intel/i82371eb/acpi/pirq.asl" + } +} |