diff options
Diffstat (limited to 'src/mainboard/asus/a8v-e_se')
| -rw-r--r-- | src/mainboard/asus/a8v-e_se/Config.lb | 190 | ||||
| -rw-r--r-- | src/mainboard/asus/a8v-e_se/Options.lb | 165 |
2 files changed, 0 insertions, 355 deletions
diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb deleted file mode 100644 index 308a1fecef..0000000000 --- a/src/mainboard/asus/a8v-e_se/Config.lb +++ /dev/null @@ -1,190 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## (Written by Yinghai Lu <yinghailu@amd.com> for AMD) -## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_ROM_PAYLOAD = 1 - -arch i386 end - -driver mainboard.o -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - mainboardinit southbridge/via/k8t890/romstrap.inc - ldscript /southbridge/via/k8t890/romstrap.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - - mainboardinit cpu/amd/car/cache_as_ram.inc - -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -config chip.h - -chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0" # Enable SB functions - register "fn_ctrl_hi" = "0xad" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard (off) - end - device pnp 2e.106 off # Serial flash - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO_PLED - end - device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 on # GPIO5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 12.0 off end # VIA LAN (off, other chip used) - end - chip southbridge/via/k8t890 # "Southbridge" K8T890 - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb deleted file mode 100644 index 92c51feb0c..0000000000 --- a/src/mainboard/asus/a8v-e_se/Options.lb +++ /dev/null @@ -1,165 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License v2 as published by -## the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -# uses CONFIG_USE_OPTION_TABLE -# uses CONFIG_RAMTOP -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -# bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -# bx_b005+ -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_USE_PRINTK_IN_CAR - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_GENERATE_PIRQ_TABLE = 0 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME -# Move the default coreboot CMOS range off of AMD RTC registers. -default CONFIG_LB_CKS_RANGE_START = 49 -default CONFIG_LB_CKS_RANGE_END = 122 -default CONFIG_LB_CKS_LOC = 123 -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_MAX_PHYSICAL_CPUS = 1 -default CONFIG_LOGICAL_CPUS = 1 -default CONFIG_GENERATE_ACPI_TABLES = 1 - -# 1G memory hole -# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 - -# Opteron K8 1G HT support -default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 - -# HT Unit ID offset, default is 1, the typical one. -default CONFIG_HT_CHAIN_UNITID_BASE = 0x0 - -# Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 - -# Make the SB HT chain on bus 0, default is not (0). -# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2 - -# bx_b005+ make the SB HT chain on bus 0. -default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1 - -# Only offset for SB chain?, default is yes(1). -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 - -default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. -default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA. -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xcc000 -default CONFIG_DCACHE_RAM_SIZE = 0x4000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 -default CONFIG_USE_INIT = 0 -default CONFIG_ENABLE_APIC_EXT_ID = 0 -default CONFIG_APIC_ID_OFFSET = 0x10 -default CONFIG_LIFT_BSP_APIC_ID = 0 -default CONFIG_IOAPIC = 1 -default CONFIG_MAINBOARD_VENDOR = "ASUS" -default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 256 * 1024 -# More 1M for pgtbl. -# default CONFIG_RAMTOP = 2048*1024 -default CONFIG_RAMBASE = 0x00004000 -# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_GDB_STUB = 0 -default CONFIG_USE_PRINTK_IN_CAR = 1 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -end |