diff options
Diffstat (limited to 'src/mainboard/asus/a8n_e/Options.lb')
| -rw-r--r-- | src/mainboard/asus/a8n_e/Options.lb | 283 |
1 files changed, 65 insertions, 218 deletions
diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb index e4eef79986..3e3f2ce03f 100644 --- a/src/mainboard/asus/a8n_e/Options.lb +++ b/src/mainboard/asus/a8n_e/Options.lb @@ -80,7 +80,6 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK - uses USE_DCACHE_RAM uses DCACHE_RAM_BASE uses DCACHE_RAM_SIZE @@ -89,233 +88,81 @@ uses DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_AP_CODE_IN_CAR uses MEM_TRAIN_SEQ uses WAIT_BEFORE_CPUS_INIT - uses ENABLE_APIC_EXT_ID uses APIC_ID_OFFSET uses LIFT_BSP_APIC_ID - uses CONFIG_PCI_64BIT_PREF_MEM - uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - uses CONFIG_LB_MEM_TOPK - -## ROM_SIZE is the size of boot ROM that this board will use. -## ---> 512 Kbytes -default ROM_SIZE=(512*1024) - -## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default FALLBACK_SIZE=(252*1024) - -#FAILOVER: 4K -default FAILOVER_SIZE=(4*1024) - -### -### Build options -### - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=13 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default HAVE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 - -##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0 - -##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x10 - -#make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 - -##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#BTEXT Console -#default CONFIG_CONSOLE_BTEXT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## enable CACHE_AS_RAM specifics -## -default USE_DCACHE_RAM=1 -#default DCACHE_RAM_BASE=0xcf000 -#default DCACHE_RAM_SIZE=0x1000 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 - -## APIC stuff -#default ENABLE_APIC_EXT_ID=0 -#default APIC_ID_OFFSET=0x10 -#default LIFT_BSP_APIC_ID=0 - - -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default MAINBOARD_PART_NUMBER="A8NE" -default MAINBOARD_VENDOR="ASUS" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891 - -### -### coreboot layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = (64*1024) -#65536 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#efault USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default _RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## +default ROM_SIZE = 512 * 1024 +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 252 * 1024 +default FAILOVER_SIZE = 4 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_FAILOVER_BOOT = 1 +default HAVE_HARD_RESET = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 13 +default HAVE_MP_TABLE = 1 +default HAVE_OPTION_TABLE = 1 +# Move the default coreboot CMOS range off of AMD RTC registers. +default LB_CKS_RANGE_START = 49 +default LB_CKS_RANGE_END = 122 +default LB_CKS_LOC = 123 +# SMP support (only worry about 2 micro processors). +default CONFIG_SMP = 1 +default CONFIG_MAX_CPUS = 2 +default CONFIG_MAX_PHYSICAL_CPUS = 1 +default CONFIG_LOGICAL_CPUS = 1 +# 1G memory hole. +default HW_MEM_HOLE_SIZEK = 0x100000 +# HT Unit ID offset, default is 1, the typical one. +default HT_CHAIN_UNITID_BASE = 0 +# Real SB Unit ID, default is 0x20, mean don't touch it at last. +# default HT_CHAIN_END_UNITID_BASE = 0x10 +# Make the SB HT chain on bus 0, default is not (0). +default SB_HT_CHAIN_ON_BUS0 = 2 +# Only offset for SB chain?, default is yes(1). +default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +# default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console +default CONFIG_CONSOLE_VGA = 1 # For VGA console +default CONFIG_PCI_ROM_RUN = 1 # For VGA console +default USE_DCACHE_RAM = 1 +default DCACHE_RAM_BASE = 0xc8000 +default DCACHE_RAM_SIZE = 32 * 1024 +default DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 +default CONFIG_USE_INIT = 0 +default CONFIG_AP_CODE_IN_CAR = 0 +default MEM_TRAIN_SEQ = 2 +default WAIT_BEFORE_CPUS_INIT = 0 +# default ENABLE_APIC_EXT_ID = 0 +# default APIC_ID_OFFSET = 0x10 +# default LIFT_BSP_APIC_ID = 0 +# default CONFIG_PCI_64BIT_PREF_MEM = 1 +default CONFIG_IOAPIC = 1 +default MAINBOARD_PART_NUMBER = "A8N-E" +default MAINBOARD_VENDOR = "ASUS" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x10f1 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x2891 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +# Only use the option table in a normal image. +default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE) +default _RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_GDB_STUB = 0 +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 +default DEFAULT_CONSOLE_LOGLEVEL = 8 +default MAXIMUM_CONSOLE_LOGLEVEL = 8 +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 - -# Select the serial console base port -default TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb end |