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-rw-r--r--src/mainboard/asrock/939a785gmh/romstage.c1
-rw-r--r--src/mainboard/asrock/e350m1/reset.c7
-rw-r--r--src/mainboard/asrock/e350m1/romstage.c1
3 files changed, 4 insertions, 5 deletions
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 46b6ab0305..74a5412caf 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -28,7 +28,6 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
diff --git a/src/mainboard/asrock/e350m1/reset.c b/src/mainboard/asrock/e350m1/reset.c
index 5958e772dd..bb2482b57b 100644
--- a/src/mainboard/asrock/e350m1/reset.c
+++ b/src/mainboard/asrock/e350m1/reset.c
@@ -17,10 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
#include <reset.h>
-#include <arch/io.h> /*inb, outb*/
-#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/
#define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5)
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 3a1e7aa0d2..79f963b529 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -24,7 +24,6 @@
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>