diff options
Diffstat (limited to 'src/mainboard/asrock/imb-1222/devicetree.cb')
| -rw-r--r-- | src/mainboard/asrock/imb-1222/devicetree.cb | 263 |
1 files changed, 263 insertions, 0 deletions
diff --git a/src/mainboard/asrock/imb-1222/devicetree.cb b/src/mainboard/asrock/imb-1222/devicetree.cb new file mode 100644 index 0000000000..c91ffaae52 --- /dev/null +++ b/src/mainboard/asrock/imb-1222/devicetree.cb @@ -0,0 +1,263 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/cannonlake + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + # CPUs over 80W will be limited due to power design + register "power_limits_config" = "{ + .tdp_pl1_override = 80, + .tdp_pl2_override = 80, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "true" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Misc + register "AcousticNoiseMitigation" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "13" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # + # With vendor firmware, MISCCFG register = 0x0e06923b + # (offset 10h, p.1234, Doc#620855-002): + # GPE0_DW0: [11:8] 2h -> GPP_C[23:0] mapped to GPE[23:0] + # GPE0_DW1: [15:12] 9h -> GPP_K[23:0] mapped to GPE[55:32] + # GPE0_DW2: [19:16] 6h -> GPP_E[23:0] mapped to GPE[87:64] + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_K" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree (override src/soc/intel/cannonlake/chipset_pch_h.cb) + device domain 0 on + subsystemid 1849 9b73 inherit + device ref peg0 on # PCIe x16 Gen3 + register "PcieClkSrcUsage[0]" = "0x41" + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCIE16X" "SlotDataBusWidth16X" + end + device ref igpu on + # FIXME: EDP should be enabled as soon as it is tested + register "DdiPortEdp" = "0" + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortDDdc" = "1" + end + device ref dptf on end + device ref thermal on end + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* Rear (USB3_1) */ + [1] = USB2_PORT_MID(OC_SKIP), /* Rear (USB3_2) */ + [2] = USB2_PORT_MID(OC_SKIP), /* Front (USB3_3) */ + [3] = USB2_PORT_MID(OC_SKIP), /* Front (USB3_4) */ + [4] = USB2_PORT_MID(OC_SKIP), /* Rear (USB3_5) */ + [5] = USB2_PORT_MID(OC_SKIP), /* Rear (USB3_6) */ + [7] = USB2_PORT_MID(OC_SKIP), /* Front (USB2_8_9) */ + [8] = USB2_PORT_MID(OC_SKIP), /* Front (USB2_8_9) */ + [10] = USB2_PORT_MID(OC_SKIP), /* Front (USB2_11_12) */ + [11] = USB2_PORT_MID(OC_SKIP), /* Front (USB2_11_12) */ + [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth (M.2 Key-E 2230) */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear (USB3_1) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear (USB3_2) */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Front (USB3_3) */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* Front (USB3_4) */ + [6] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear (USB3_5) */ + [7] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear (USB3_6) */ + }" + # ACPI (src/drivers/usb/acpi/usb_acpi.c) + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3_1 Type-A Rear Top"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3_1 Type-A Rear Top"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3_2 Type-A Rear Bottom"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3_2 Type-A Rear Bottom"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3_3 Type-A Front"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3_3 Type-A Front"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3_4 Type-A Front"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3_4 Type-A Front"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device ref usb3_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3_5 Type-A Rear Top"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 4)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3_5 Type-A Rear Top"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 4)" + device ref usb3_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3_6 Type-A Rear Bottom"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 5)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3_6 Type-A Rear Bottom"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 5)" + device ref usb3_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2_8 Front"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 6)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2_9 Front"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 7)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2_11 Front"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 8)" + device ref usb2_port11 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2_12 Front"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 9)" + device ref usb2_port12 on end + end + chip drivers/usb/acpi + register "desc" = ""M.2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 10)" + device ref usb2_port14 on end + end + end + end + end + device ref shared_sram on end + device ref cnvi_wifi on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (CNVi) + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end + device ref sata on + register "SataPortsEnable" = "{ + [1] = 1, /* SATA 3_1 */ + [2] = 1, /* SATA 3_2 */ + [4] = 1, /* M.2 Key-M 2242/2260/2280 slot for SSD (SATA) */ + }" + end + device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4) + register "PcieRpEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "1" + register "PcieRpSlotImplemented[16]" = "1" + register "PcieClkSrcUsage[7]" = "16" + register "PcieClkSrcClkReq[7]" = "7" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2242/2260/2280 (M2_KEYM1)" "SlotDataBusWidth4X" + end + device ref pcie_rp5 on # Intel Corporation Ethernet Controller I225-LM + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[3]" = "4" + register "PcieClkSrcClkReq[3]" = "3" + end + device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1) + register "PcieRpEnable[5]" = "1" + register "PcieRpSlotImplemented[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[5]" = "5" + register "PcieClkSrcClkReq[5]" = "5" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X" + end + device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1) + register "PcieRpEnable[6]" = "1" + register "PcieRpSlotImplemented[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieClkSrcUsage[6]" = "6" + register "PcieClkSrcClkReq[6]" = "6" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/B 3042/3052 (M2_KEYB1)" "SlotDataBusWidth1X" + end + device ref lpc_espi on + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0281" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + + # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref hda on + register "PchHdaAudioLinkHda" = "1" + end + device ref smbus on end + device ref gbe on + register "PcieClkSrcUsage[4]" = "PCIE_CLK_LAN" + register "PcieClkSrcClkReq[4]" = "4" + end + end +end |