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-rw-r--r--src/mainboard/asrock/e350m1/Kconfig15
-rw-r--r--src/mainboard/asrock/e350m1/acpi/ssdt2.asl84
-rw-r--r--src/mainboard/asrock/e350m1/acpi/ssdt3.asl84
-rw-r--r--src/mainboard/asrock/e350m1/acpi/ssdt4.asl84
-rw-r--r--src/mainboard/asrock/e350m1/acpi/ssdt5.asl85
-rw-r--r--src/mainboard/asrock/e350m1/devicetree.cb42
-rw-r--r--src/mainboard/asrock/e350m1/dimmSpd.c4
-rw-r--r--src/mainboard/asrock/e350m1/dsdt.asl4
-rw-r--r--src/mainboard/asrock/e350m1/mainboard.c10
-rw-r--r--src/mainboard/asrock/e350m1/mptable.c2
-rw-r--r--src/mainboard/asrock/e350m1/romstage.c6
11 files changed, 49 insertions, 371 deletions
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index 650e7aa543..06fd4f0f34 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -17,7 +17,7 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-if BOARD_AMD_PERSIMMON
+if BOARD_ASROCK_E350M1
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -28,7 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
- select SUPERIO_FINTEK_F81865F
+ select SUPERIO_WINBOND_W83627HF
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
@@ -56,7 +56,7 @@ config AMD_CIMX_SB800
config MAINBOARD_DIR
string
- default amd/persimmon
+ default asrock/e350m1
config APIC_ID_OFFSET
hex
@@ -64,7 +64,7 @@ config APIC_ID_OFFSET
config MAINBOARD_PART_NUMBER
string
- default "Persimmon"
+ default "E350M1"
config HW_MEM_HOLE_SIZEK
hex
@@ -132,16 +132,15 @@ config RAMBASE
config SIO_PORT
hex
- default 0x4e
+ default 0x2e
config ONBOARD_VGA_IS_PRIMARY
bool
default y
-#define CONFIG_VGA_BIOS_ID "1002,9804"
config VGA_BIOS_ID
string
- default "1002,9804"
+ default "1002,9802"
config DRIVERS_PS2_KEYBOARD
bool
@@ -151,5 +150,5 @@ config WARNINGS_ARE_ERRORS
bool
default n
-endif # BOARD_AMD_PERSIMMON
+endif # BOARD_ASROCK_E350M1
diff --git a/src/mainboard/asrock/e350m1/acpi/ssdt2.asl b/src/mainboard/asrock/e350m1/acpi/ssdt2.asl
deleted file mode 100644
index ef1a4bf9eb..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/ssdt2.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci2_hc.asl"
- }
- }
-
-}
-
diff --git a/src/mainboard/asrock/e350m1/acpi/ssdt3.asl b/src/mainboard/asrock/e350m1/acpi/ssdt3.asl
deleted file mode 100644
index 68a4b95abe..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/ssdt3.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci3_hc.asl"
- }
- }
-
-}
-
diff --git a/src/mainboard/asrock/e350m1/acpi/ssdt4.asl b/src/mainboard/asrock/e350m1/acpi/ssdt4.asl
deleted file mode 100644
index e06fe8ab85..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/ssdt4.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci4_hc.asl"
- }
- }
-
-}
-
diff --git a/src/mainboard/asrock/e350m1/acpi/ssdt5.asl b/src/mainboard/asrock/e350m1/acpi/ssdt5.asl
deleted file mode 100644
index a141a378d2..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/ssdt5.asl
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- #include "acpi/pci5_hc.asl"
- }
- }
-
-}
-
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 48fd741ec8..648db989c1 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -55,30 +55,46 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
- chip superio/fintek/f81865f
- device pnp 4e.0 off # Floppy
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
- device pnp 4e.3 off end # Parallel Port
- device pnp 4e.4 off end # Hardware Monitor
- device pnp 4e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
end
- device pnp 4e.6 off end # GPIO
- device pnp 4e.a off end # PME
- device pnp 4e.10 on # COM1
+ device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 4e.11 off # COM2
+ device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
- end # f81865f
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
end #LPC
device pci 14.4 on end # PCI 0x4384
device pci 14.5 on end # USB 2
diff --git a/src/mainboard/asrock/e350m1/dimmSpd.c b/src/mainboard/asrock/e350m1/dimmSpd.c
index 94e63e1bda..8ef1b4c650 100644
--- a/src/mainboard/asrock/e350m1/dimmSpd.c
+++ b/src/mainboard/asrock/e350m1/dimmSpd.c
@@ -34,8 +34,8 @@ static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm
{
// socket 0
{
- {0xA0, 0xA2}, // channel 0 dimms
- {0xA4, 0xA8}, // channel 1 dimms
+ {0xA0, 0xA4}, // channel 0 dimms
+ {0x00, 0x00}, // channel 1 dimms
},
// socket 1
{
diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl
index 71a6189964..32d4497b42 100644
--- a/src/mainboard/asrock/e350m1/dsdt.asl
+++ b/src/mainboard/asrock/e350m1/dsdt.asl
@@ -22,8 +22,8 @@ DefinitionBlock (
"DSDT.AML", /* Output filename */
"DSDT", /* Signature */
0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "AMD ", /* OEMID */
- "PERSIMMO", /* TABLE ID */
+ "ASROCK", /* OEMID */
+ "E350M1 ", /* TABLE ID */
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index cf478fbaf7..4e5832426e 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -49,11 +49,11 @@ void set_pcie_dereset(void)
uint64_t uma_memory_base, uma_memory_size;
/*************************************************
-* enable the dedicated function in persimmon board.
+* enable the dedicated function in e350m1 board.
*************************************************/
-static void persimmon_enable(device_t dev)
+static void e350m1_enable(device_t dev)
{
- printk(BIOS_INFO, "Mainboard Persimmon Enable. dev=0x%p\n", dev);
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
#if (CONFIG_GFXUMA == 1)
msr_t msr, msr2;
uint32_t sys_mem;
@@ -110,6 +110,6 @@ int add_mainboard_resources(struct lb_memory *mem)
return 0;
}
struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD PERSIMMON Mainboard")
- .enable_dev = persimmon_enable,
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = e350m1_enable,
};
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 0296cebff8..78eec6a14a 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
+ memcpy(mc->mpc_oem, "ASROCK ", 8);
smp_write_processors(mc);
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index c1655b04ff..b48a58af6b 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -31,7 +31,7 @@
#include <console/loglevel.h>
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
-#include "superio/fintek/f81865f/f81865f_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "pc80/i8254.c"
#include "pc80/i8259.c"
@@ -40,7 +40,7 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
+#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -52,7 +52,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb_poweron_init();
post_code(0x31);
- f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 08:13:47 +0000