diff options
Diffstat (limited to 'src/mainboard/arima/hdama/auto.c')
-rw-r--r-- | src/mainboard/arima/hdama/auto.c | 51 |
1 files changed, 43 insertions, 8 deletions
diff --git a/src/mainboard/arima/hdama/auto.c b/src/mainboard/arima/hdama/auto.c index b4d955385f..7790b3ea50 100644 --- a/src/mainboard/arima/hdama/auto.c +++ b/src/mainboard/arima/hdama/auto.c @@ -11,6 +11,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" +#include "northbridge/amd/amdk8/cpu_rev.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -18,28 +19,59 @@ #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" -#include "northbridge/amd/amdk8/cpu_rev.c" #include "superio/NSC/pc87360/pc87360_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { - set_bios_reset(); + device_t dev; + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); + /* reset */ + set_bios_reset(); outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + + /* Reset */ set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } /* @@ -128,6 +160,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" #include "northbridge/amd/amdk8/resourcemap.c" +#include "debug.c" #define FIRST_CPU 1 #define SECOND_CPU 1 @@ -160,13 +193,14 @@ static void main(unsigned long bist) }; int needs_reset; - unsigned nodeid; if (bist == 0) { + unsigned nodeid; /* Skip this if there was a built in self test failure */ amd_early_mtrr_init(); enable_lapic(); init_timer(); nodeid = lapicid() & 0xf; + /* Has this cpu already booted? */ if (cpu_init_detected(nodeid)) { asm volatile ("jmp __cpu_reset"); @@ -191,13 +225,12 @@ static void main(unsigned long bist) print_info("ht reset -\r\n"); soft_reset(); } - #if 0 print_pci_devices(); #endif enable_smbus(); #if 0 - dump_spd_registers(&cpu[0]); + dump_spd_registers(sizeof(cpu)/sizeof(cpu[0]), cpu); #endif memreset_setup(); @@ -205,6 +238,8 @@ static void main(unsigned long bist) #if 0 dump_pci_devices(); +#endif +#if 0 dump_pci_device(PCI_DEV(0, 0x18, 2)); #endif |