diff options
Diffstat (limited to 'src/mainboard/apple')
| -rw-r--r-- | src/mainboard/apple/macbook21/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/apple/macbook21/romstage.c | 110 |
2 files changed, 5 insertions, 109 deletions
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 5ce28a27a9..137c8fc929 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -77,6 +77,10 @@ chip northbridge/intel/i945 register "c3_latency" = "0x23" register "p_cnt_throttling_supported" = "1" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen4_dec" = "0x001c0301" + device pci 1b.0 on # Audio Controller subsystemid 0x8384 0x7680 end diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 34cd378839..aced71ce6a 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -27,114 +27,6 @@ #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/pmclib.h> -static void ich7_enable_lpc(void) -{ - /* Enable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - - /* I/O Decode Ranges - * X60: 0x0210 == 00000010 00010000 - * Macbook21: 0x0010 == 00000000 00010000 - * Bit 9:8 LPT Decode Range. This field determines which range to - * decode for the LPT Port. - * 00 = 378h - 37Fh and 778h - 77Fh - * 10 = 3BCh - 3BEh and 7BCh - 7BEh - */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - - /* LPC_EN--LPC I/F Enables Register - * X60: 0x1f0d == 00011111 00001101 - * Macbook21: 0x3807 == 00111000 00000111 - * Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 4Eh and 4Fh - * to the LPC interface. This range is used for a - * microcontroller. - * Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 2Eh and 2Fh - * to the LPC interface. This range is used for - * Super I/O devices. - * Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 62h and 66h - * to the LPC interface. This range is used for a - * microcontroller. - * Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 60h and 64h - * to the LPC interface. This range is used for a - * microcontroller. - * Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 208h to 20Fh - * to the LPC interface. This range is used for a gameport. - * Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 200h to 207h - * to the LPC interface. This range is used for a gameport. - * Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable - * 0 = Disable. - * 1 = Enables the decoding of the FDD range to the LPC - * interface. This range is selected in the LPC_FDD/LPT - * Decode Range Register (D31:F0:80h, bit 12). - * Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable - * 0 = Disable. - * 1 = Enables the decoding of the LPT range to the LPC - * interface. This range is selected in the LPC_FDD/LPT - * Decode Range Register (D31:F0:80h, bit 9:8). - * Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable - * 0 = Disable. - * 1 = Enables the decoding of the COMB range to the LPC - * interface. This range is selected in the LPC_COM Decode - * Range Register (D31:F0:80h, bits 6:4). - * Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable - * 0 = Disable. - * 1 = Enables the decoding of the COMA range to the LPC - * interface. This range is selected in the LPC_COM Decode - * Range Register (D31:F0:80h, bits 3:2). - */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN - | CNF1_LPC_EN | MC_LPC_EN | LPT_LPC_EN | COMB_LPC_EN - | COMA_LPC_EN); - - /* GEN1_DEC, LPC Interface Generic Decode Range 1 - * X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 - * Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 - * Bit 31:24 Reserved. - * Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any - * bit position indicates that any value in the corresponding - * address bit in a received cycle will be treated as a - * match. The corresponding bit in the Address field, below, - * is ignored. The mask is only provided for the lower 6 bits - * of the DWord address, allowing for decoding blocks up to - * 256 bytes in size. - * Bit 17:16 Reserved. - * Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This - * address is aligned on a 128-byte boundary, and must have - * address lines 31:16 as 0. NOTE: The Intel ICH7 does not - * provide decode down to the word or byte level. - * Bit 1 Reserved. - * Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. - * 0 = Disable. - * 1 = Enable the GEN1 I/O range to be forwarded to the LPC - * I/F - */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0681); - - /* GEN2_DEC, LPC Interface Generic Decode Range 2 - * X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 - * Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 - */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c1641); - - /* GEN4_DEC, LPC Interface Generic Decode Range 4 - * X60: 0x0000 0x0000 - * Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 - */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x001c0301); -} - static void rcba_config(void) { /* V0CTL Virtual Channel 0 Resource Control */ @@ -205,7 +97,7 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); /* Set up the console */ console_init(); |