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Diffstat (limited to 'src/mainboard/aopen/dxplplusu/acpi')
-rw-r--r--src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl68
-rw-r--r--src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl56
-rw-r--r--src/mainboard/aopen/dxplplusu/acpi/i82801db.asl166
-rw-r--r--src/mainboard/aopen/dxplplusu/acpi/p64h2.asl76
-rw-r--r--src/mainboard/aopen/dxplplusu/acpi/power.asl71
-rw-r--r--src/mainboard/aopen/dxplplusu/acpi/scsi.asl29
-rw-r--r--src/mainboard/aopen/dxplplusu/acpi/superio.asl161
7 files changed, 627 insertions, 0 deletions
diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl
new file mode 100644
index 0000000000..aab327134a
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (MBRS)
+{
+ Name (_HID, EisaId ("PNP0C01"))
+ Name (_UID, 0x01)
+ Name (MSBF, ResourceTemplate ()
+ {
+ /* System memory */
+ QWordMemory (ResourceProducer, PosDecode, MinFixed,
+ MaxNotFixed, Prefetchable, ReadWrite,
+ 0x0, 0x100000000, 0x400000000, 0x0, 0x0, ,, _Y1C,
+ AddressRangeMemory, TypeStatic)
+
+ /* Top Of Low Memory */
+ Memory32 (ReadOnly, 0x0, 0x0, 0x1, 0x0, _Y1D)
+
+ /* 640kB who wants more? */
+ Memory32Fixed (ReadWrite, 0x0, 0xA0000, )
+
+ /* 64k BIOS bootblock */
+ Memory32Fixed (ReadOnly, 0xF0000, 0x10000,)
+
+ /* ISA memory hole 15-16 MB ? */
+ /* Memory32Fixed (ReadOnly, 0x100000, 0xF00000,) */
+ /* ISA memory hole 14-15 MB ? */
+ /* Memory32Fixed (ReadOnly, 0x100000, 0xE00000,) */
+
+ /* Local APIC */
+ Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000,)
+ })
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateQWordField (MSBF, \_SB.MBRS._Y1C._MIN, MEML)
+ CreateQWordField (MSBF, \_SB.MBRS._Y1C._MAX, MEMM)
+ CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM)
+
+ And (\_SB.PCI0.RLAR, 0x03FF, Local1)
+ Local1++
+ If (Local1 > 0x40)
+ {
+ ShiftLeft (Local1, 0x1A, LELM)
+ }
+
+
+ CreateDWordField (MSBF, \_SB.MBRS._Y1D._MIN, MS00)
+ CreateDWordField (MSBF, \_SB.MBRS._Y1D._MAX, MS01)
+ CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2)
+ And (\_SB.PCI0.TOLM, 0xF800, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ Local1--
+ If (Local1 > 0x10)
+ {
+ Local1 -= 0x0F
+ Store (ShiftLeft (Local1, 0x14), MEM2)
+ Store (0x01000000, MS00)
+ Store (MS00, MS01)
+ }
+
+ Return (MSBF)
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl
new file mode 100644
index 0000000000..400a5d7092
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/ioapic.h>
+
+Name (PBRS, ResourceTemplate ()
+{
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100, ,, )
+
+ /* System IO */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0, 0x0, 0xffff, 0x0000, 0x10000, ,,, TypeStatic)
+ IO (Decode16, 0x0CF8, 0x0CF8, 0x08, 0x08, )
+
+ /* Video RAM */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, 0x000A0000, 0x000BFFFF,
+ 0x00000000, 0x00020000, ,,, AddressRangeMemory, TypeStatic)
+
+ /* Video ROM */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, 0x000C0000, 0x000C7FFF,
+ 0x00000000, 0x00008000, ,,, AddressRangeMemory, TypeStatic)
+
+ /* Option ROMs ? */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, 0x000C8000, 0x000DFFFF,
+ 0x00000000, 0x00018000, ,,, AddressRangeMemory, TypeStatic)
+
+ /* Top Of Lowmemory to IOAPIC */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0xFEBFFFFF,
+ 0x00000000, IO_APIC_ADDR, ,, _Y08, AddressRangeMemory, TypeStatic)
+})
+
+
+Method (_CRS, 0, NotSerialized)
+{
+
+ /* Top Of Lowmemory to IOAPIC */
+ CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML)
+ CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH)
+ CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM)
+ And (\_SB.PCI0.TOLM, 0xF800, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ ShiftLeft (Local1, 0x14, MEML)
+ MEMH = IO_APIC_ADDR - 1
+ LENM = IO_APIC_ADDR - MEML
+
+ Return (PBRS)
+}
+
+Method (_STA, 0, NotSerialized)
+{
+ Return (0x0F)
+}
diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl
new file mode 100644
index 0000000000..9b16070167
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl
@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/ioapic.h>
+
+Device (USB0)
+{
+ Name (_ADR, 0x001D0000)
+ Name (_PRW, Package () { 0x03, 0x05 })
+
+ OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
+ Field (USBS, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xC4), URES, 8
+ }
+}
+
+Device (USB1)
+{
+ Name (_ADR, 0x001D0001)
+ Name (_PRW, Package () { 0x04, 0x05 })
+ OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
+ Field (USBS, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xC4), URES, 8
+ }
+}
+
+Device (USB2)
+{
+ Name (_ADR, 0x001D0002)
+ Name (_PRW, Package () { 0x0C, 0x05 })
+ OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
+ Field (USBS, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xC4), URES, 8
+ }
+}
+
+Device (USB3)
+{
+ Name (_ADR, 0x001D0007)
+ Name (_PRW, Package () { 0x0D, 0x05 }) /* PME_B0_STS any 0:1d or 0:1f device */
+ OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
+ Field (USBS, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xC4), URES, 8
+ }
+}
+
+Device(PCI5)
+{
+ Name (_ADR, 0x001E0000)
+ Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
+ Name (_PRT, Package() {
+ Package() { 0x0003ffff, 0, 0, 20 },
+ Package() { 0x0003ffff, 1, 0, 21 },
+ Package() { 0x0003ffff, 2, 0, 22 },
+ Package() { 0x0003ffff, 3, 0, 23 },
+ })
+}
+
+Device (ICH0)
+{
+ Name (_ADR, 0x001F0000)
+ OperationRegion (D310, PCI_Config, 0x00, 0xFF)
+ Field (D310, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x40), PBAR, 16,
+ Offset (0x58), GBAR, 16,
+ }
+
+ OperationRegion (ACPI, SystemIO, 0x0400, 0xC0)
+ Field (ACPI, ByteAcc, NoLock, Preserve)
+ {
+ PS1L, 8,
+ PS1H, 8,
+ PE1L, 8,
+ PE1H, 8,
+
+ Offset (0x28),
+ GS0L, 8,
+ GS0H, 8,
+ GSPL, 8,
+ GSPH, 8,
+ GE0L, 8,
+ GE0H, 8,
+ GEPL, 8,
+ GEPH, 8,
+
+ Offset (0xB8),
+ GPLV, 8
+ }
+
+ Name (MSBF, ResourceTemplate ()
+ {
+ /* IOAPIC 0 */
+ Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000,)
+
+ IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO)
+ IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO)
+
+ /* 8254 legacy irq */
+ IO (Decode16, 0x04D0, 0x04D0, 0x02, 0x02,)
+
+ /* reset generator */
+ IO (Decode16, 0x0092, 0x0092, 0x01, 0x01, )
+ })
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MIN, IOA1)
+ CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MAX, IOA2)
+ CreateByteField (MSBF, \_SB_.PCI0.ICH0.PMIO._LEN, IOAL)
+
+ Store (PBAR, Local0)
+ If (Local0 && 1)
+ {
+ And (Local0, 0xFFFE, Local0)
+ Store (Local0, IOA1)
+ Store (Local0, IOA2)
+ Store (0x80, IOAL)
+ } Else {
+ Store (0x00, IOAL)
+ }
+
+ CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MIN, IOS1)
+ CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MAX, IOS2)
+ CreateByteField (MSBF, \_SB_.PCI0.ICH0.GPIO._LEN, IOSL)
+
+ Store (GBAR, Local0)
+ If (Local0 && 1) {
+ And (Local0, 0xFFFE, Local0)
+ Store (Local0, IOS1)
+ Store (Local0, IOS2)
+ Store (0x40, IOSL)
+ } Else {
+ Store (0x00, IOSL)
+ }
+ Return (MSBF)
+ }
+
+ Device (FWH)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x01)
+
+
+ Name (MSBG, ResourceTemplate () {
+ Memory32Fixed (ReadOnly, 0xFFF00000, 0x00080000,)
+ Memory32Fixed (ReadOnly, 0xFFF80000, 0x00080000,)
+ })
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Return (MSBG)
+ }
+ }
+
+ Device (SMSC)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x02)
+ #include "acpi/superio.asl"
+ }
+
+}
diff --git a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl
new file mode 100644
index 0000000000..9a3e1b5aa7
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Interrupt routing for PCI 03:xx.x */
+
+/* I/O APIC id 0x3 */
+Device(PBIO)
+{
+ Name (_ADR, 0x001c0000)
+}
+
+/* PCI-X bridge */
+Device(P64B)
+{
+ Name (_ADR, 0x001d0000)
+ Name (_PRT, Package() {
+ Package() { 0x0002ffff, 0, 0, 24 }, /* PCI-X slot 1 */
+ Package() { 0x0002ffff, 1, 0, 25 },
+ Package() { 0x0002ffff, 2, 0, 26 },
+ Package() { 0x0002ffff, 3, 0, 27 },
+ Package() { 0x0003ffff, 0, 0, 28 }, /* PCI-X slot 2 */
+ Package() { 0x0003ffff, 1, 0, 29 },
+ Package() { 0x0003ffff, 2, 0, 30 },
+ Package() { 0x0003ffff, 3, 0, 31 },
+ Package() { 0x0004ffff, 0, 0, 32 }, /* On-board GbE */
+ })
+
+ Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
+ OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)
+ Field (PBPC, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x3E), BCRL, 8, BCRH, 8
+ }
+
+
+ Device (ETH0)
+ {
+ Name (_ADR, 0x00040000)
+ Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
+ }
+}
+
+
+/* Interrupt routing for PCI 04:xx.x */
+
+/* I/O APIC id 0x4 */
+Device(PAIO)
+{
+ Name (_ADR, 0x001e0000)
+}
+
+/* PCI-X bridge */
+Device(P64A)
+{
+ Name (_ADR, 0x001f0000)
+ Name (_PRT, Package() {
+ Package() { 0x0002ffff, 0, 0, 48 }, /* PCI-X slot 3 */
+ Package() { 0x0002ffff, 1, 0, 49 },
+ Package() { 0x0002ffff, 2, 0, 50 },
+ Package() { 0x0002ffff, 3, 0, 51 },
+ Package() { 0x0003ffff, 0, 0, 52 }, /* PCI-X slot 4 */
+ Package() { 0x0003ffff, 1, 0, 53 },
+ Package() { 0x0003ffff, 2, 0, 54 },
+ Package() { 0x0003ffff, 3, 0, 55 },
+ Package() { 0x0004ffff, 0, 0, 54 }, /* On-board SCSI, GSI not 56 ? */
+ Package() { 0x0004ffff, 1, 0, 55 }, /* On-board SCSI, GSI not 57 */
+ })
+
+ Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
+ OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)
+ Field (PBPC, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x3E), BCRL, 8, BCRH, 8
+ }
+
+ #include "acpi/scsi.asl"
+}
diff --git a/src/mainboard/aopen/dxplplusu/acpi/power.asl b/src/mainboard/aopen/dxplplusu/acpi/power.asl
new file mode 100644
index 0000000000..903d844d42
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/acpi/power.asl
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+/* Board powers on with button or PME# from on-board GbE wake-on-lan.
+ * Board shuts down to S5/G2. Any other power management is untested.
+ */
+
+Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 })
+Name (\_S3, Package () { 0x05, 0x05, 0x00, 0x00 })
+Name (\_S4, Package () { 0x06, 0x06, 0x00, 0x00 })
+Name (\_S5, Package () { 0x07, 0x07, 0x00, 0x00 })
+
+Scope (\_GPE)
+{
+ Method (_L03, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0.USB0, 0x02)
+ }
+ Method (_L04, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0.USB1, 0x02)
+ }
+
+ /* WOL header */
+ Method (_L08, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0.PCI5, 0x02)
+ Notify (\_SB.SLBT, 0x02)
+ }
+
+ /* PME# */
+ Method (_L0B, 0, NotSerialized)
+ {
+ Notify (\_SB.LID0, 0x02)
+ }
+
+ Method (_L0C, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0.USB2, 0x02)
+ }
+
+ /* PME_B0_STS# */
+ Method (_L0D, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0.USB3, 0x02)
+ }
+}
+
+/* Clear power buttons */
+Method (\_INI, 0, NotSerialized)
+{
+ Or (\_SB.PCI0.ICH0.PS1H, 0x09, \_SB.PCI0.ICH0.PS1H)
+ Or (\_SB.PCI0.ICH0.PE1H, 0x01, \_SB.PCI0.ICH0.PE1H)
+}
+
+/* Prepare To Sleep */
+Method (\_PTS, 1, NotSerialized)
+{
+ Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H)
+ Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L)
+}
+
+/* System Wake */
+Method (\_WAK, 1, NotSerialized)
+{
+ Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H)
+ Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L)
+
+ Return ( Package() { 0x0, 0x0 } )
+}
diff --git a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl
new file mode 100644
index 0000000000..c34dd4ef0c
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* PCI-X devices 04:04.0 and 04:04.1 : AIC-7902W
+ * U320 SCSI dual-channel controller
+ */
+
+Device (SCS0)
+{
+ Name (_ADR, 0x00040000)
+ OperationRegion (SCSC, PCI_Config, 0x00, 0x0100)
+ Field (SCSC, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x2C), SID, 32,
+ Offset (0xE0), PMC, 8,
+ Offset (0xFF), IDW, 8
+ }
+}
+
+Device (SCS1)
+{
+ Name (_ADR, 0x00040001)
+ OperationRegion (SCSC, PCI_Config, 0x00, 0x0100)
+ Field (SCSC, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x2C), SID, 32,
+ Offset (0xE0), PMC, 8,
+ Offset (0xFF), IDW, 8
+ }
+}
diff --git a/src/mainboard/aopen/dxplplusu/acpi/superio.asl b/src/mainboard/aopen/dxplplusu/acpi/superio.asl
new file mode 100644
index 0000000000..b49ef444a1
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/acpi/superio.asl
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+/* SuperIO GPIO configuration via logical device 0x0A */
+
+Name (MSBF, ResourceTemplate ()
+{
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x80, _Y1B)
+})
+
+OperationRegion (LPC0, SystemIO, 0x0E00, 0x60)
+Field (LPC0, ByteAcc, NoLock, Preserve)
+{
+ PME0, 8,
+ Offset (0x02), PME2,8,
+ Offset (0x04), PME4,8,
+ Offset (0x0A), PMEA,8,
+ Offset (0x23),
+ GC10,8, GC11,8, GC12,8, GC13,8, GC14,8, GC15,8, GC16,8, GC17,8,
+ GC20,8, GC21,8, GC22,8, GC23,8, GC24,8, GC25,8, GC26,8, GC27,8,
+ GC30,8, GC31,8, GC32,8, GC33,8, GC34,8, GC35,8, GC36,8, GC37,8,
+ GC40,8, GC41,8, GC42,8, GC43,8,
+
+ Offset (0x3F),
+ GC50,8, GC51,8, GC52,8, GC53,8, GC54,8, GC55,8, GC56,8, GC57,8,
+ GC60,8, GC61,8,
+
+ Offset (0x4B),
+ GP_1,8, GP_2,8, GP_3,8, GP_4,8, GP_5,8, GP_6,8,
+ Offset (0x56), FAN1,8,
+ Offset (0x5D), LED1,8, LED2,8,
+}
+
+OperationRegion (SMC1, SystemIO, 0x2E, 0x02)
+Field (SMC1, ByteAcc, NoLock, Preserve)
+{
+ INDX, 8, DATA, 8
+}
+
+IndexField (INDX, DATA, ByteAcc, NoLock, Preserve)
+{
+ Offset (0x07), LDN, 8,
+ Offset (0x22), PWRC, 8,
+ Offset (0x30), ACTR, 8,
+ Offset (0x60),
+ IOAH, 8, IOAL, 8,
+ IOBH, 8, IOBL, 8,
+
+ Offset (0x70), INTR, 8,
+ Offset (0x72), INT1, 8,
+ Offset (0x74), DMCH, 8,
+ Offset (0xB2), SPS1, 8, SPS2, 8,
+ Offset (0xB8), D2TS, 8,
+ Offset (0xF0), OPT1, 8, OPT2, 8, OPT3, 8,
+ Offset (0xF4), WDTC, 8,
+ Offset (0xF6), GP01, 8, GP02, 8, GP04, 8
+}
+
+Method (ECFG, 0, NotSerialized)
+{
+ Store (0x55, INDX)
+}
+Method (XCFG, 0, NotSerialized)
+{
+ Store (0xAA, INDX)
+}
+
+Method (_CRS, 0, NotSerialized)
+{
+ CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MIN, IOM1)
+ CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MAX, IOM2)
+ CreateByteField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._LEN, IOML)
+
+ ECFG ()
+ Store (0x0A, \_SB.PCI0.ICH0.SMSC.LDN)
+ Store (0x00, IOM1)
+ Store (0x00, IOM2)
+ Or (\_SB.PCI0.ICH0.SMSC.IOAH, IOM1, IOM1)
+ ShiftLeft (IOM1, 0x08, IOM1)
+ Or (\_SB.PCI0.ICH0.SMSC.IOAL, IOM1, IOM1)
+ Store (IOM1, IOM2)
+ If (IOM1 != 0)
+ {
+ Store (0x80, IOML)
+ }
+ XCFG ()
+
+ Return (MSBF)
+}
+
+
+Method (_INI, 0, NotSerialized)
+{
+ /* GPIO configuration */
+ Store (0x00, GC10)
+ Store (0x81, GC11)
+ Store (0x00, GC17)
+ Store (0x0c, GC21)
+ Store (0x00, GC22)
+ Store (0x04, GC27)
+ Store (0x04, GC30)
+ Store (0x01, GC31)
+ Store (0x01, GC32)
+ Store (0x01, GC33)
+ Store (0x01, GC34) /* GPI password jumper */
+ Store (0x01, GC35) /* GPI scsi enable jumper */
+ Store (0x01, GC42) /* GPI */
+ Store (0x86, GC60) /* led 1 */
+ Store (0x81, GC61) /* led 2 ?? */
+
+ /* GPIO initial output levels */
+ Store (GP_1, Local0)
+ And( Local0, 0x7C, Local0)
+ Or ( Local0, 0x81, Local0)
+ Store (Local0, GP_1)
+
+ Store (GP_2, Local0)
+ And( Local0, 0xFE, Local0)
+ Or ( Local0, 0x00, Local0)
+ Store (Local0, GP_2)
+
+ Store (GP_3, Local0)
+ And( Local0, 0x7F, Local0)
+ Or ( Local0, 0x80, Local0)
+ Store (Local0, GP_3)
+
+ Store (GP_4, Local0)
+ And( Local0, 0x7F, Local0)
+ Or ( Local0, 0x00, Local0)
+ Store (Local0, GP_4)
+
+ /* Power Led */
+ Store (LED1, Local0)
+ And( Local0, 0xfc, Local0)
+ Or ( Local0, 0x01, Local0)
+ Store (Local0, LED1)
+
+}
+
+Method (MLED, 1, NotSerialized)
+{
+ If (LEqual (Arg0, 0x00))
+ {
+ Store (0x00, LED1)
+ }
+
+ If (LEqual (Arg0, 0x01) || LEqual (Arg0, 0x02))
+ {
+ Store (0x01, LED1)
+ }
+
+ If (LEqual (Arg0, 0x03))
+ {
+ Store (0x02, LED1)
+ }
+
+ If (LEqual (Arg0, 0x04) || LEqual (Arg0, 0x05))
+ {
+ Store (0x03, LED1)
+ }
+}