diff options
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/olivehillplus/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/amd/olivehillplus/dsdt.asl | 10 | ||||
| -rw-r--r-- | src/mainboard/amd/olivehillplus/mptable.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/olivehillplus/romstage.c | 2 |
4 files changed, 9 insertions, 9 deletions
diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb index 65f7ee4577..8dd067128f 100644 --- a/src/mainboard/amd/olivehillplus/devicetree.cb +++ b/src/mainboard/amd/olivehillplus/devicetree.cb @@ -41,7 +41,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 - chip southbridge/amd/pi/avalon # it is under NB/SB Link, but on the same pci bus + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus device pci 10.0 on end # XHCI HC0 device pci 11.0 on end # SATA device pci 12.0 on end # USB @@ -60,7 +60,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 14.3 on end # LPC 0x439d device pci 14.7 on end # SD device pci 16.0 on end # USB - end #chip southbridge/amd/pi/avalon + end #chip southbridge/amd/pi/hudson device pci 18.0 on end device pci 18.1 on end diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl index 56381e18f3..68ed74e84a 100644 --- a/src/mainboard/amd/olivehillplus/dsdt.asl +++ b/src/mainboard/amd/olivehillplus/dsdt.asl @@ -37,13 +37,13 @@ DefinitionBlock ( #include "acpi/usb_oc.asl" /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/pi/avalon/acpi/pcie.asl> + #include <southbridge/amd/pi/hudson/acpi/pcie.asl> /* Describe the processor tree (\_PR) */ #include <cpu/amd/pi/00730F01/acpi/cpu.asl> /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/pi/avalon/acpi/sleepstates.asl> + #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl> /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ #include "acpi/sleep.asl" @@ -68,16 +68,16 @@ DefinitionBlock ( #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/pi/avalon/acpi/fch.asl> + #include <southbridge/amd/pi/hudson/acpi/fch.asl> } /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/pi/avalon/acpi/pci_int.asl> + #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> } /* End \_SB scope */ /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/pi/avalon/acpi/smbus.asl> + #include <southbridge/amd/pi/hudson/acpi/smbus.asl> /* Define the General Purpose Events for the platform */ #include "acpi/gpe.asl" diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 80ba5b5af7..d49c998332 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -27,7 +27,7 @@ #include <cpu/amd/amdfam15.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <southbridge/amd/pi/avalon/hudson.h> /* pm_ioread() */ +#include <southbridge/amd/pi/hudson/hudson.h> /* pm_ioread() */ u8 picr_data[0x54] = { 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 63044ed4d0..6b081c653e 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -34,7 +34,7 @@ #include <northbridge/amd/pi/agesawrapper_call.h> #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> -#include <southbridge/amd/pi/avalon/hudson.h> +#include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |