8 files changed, 27 insertions, 19 deletions
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
index 88af2b7302..564d196428 100644..100755
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -31,3 +31,7 @@ ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
 ramstage-y += pmio.c
+
+AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../../$(AGESA_ROOT)
+#subdirs-$(CONFIG_AMD_CIMX) += ../../../vendorcode/amd/cimx
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index 9d471d029a..0ccef102f3 100644
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -25,11 +25,10 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-#define SMBUS_IO_BASE 0x6000
-
 uint64_t uma_memory_base, uma_memory_size;
 
 void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index b4c9635fe9..5c9d5383c2 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -44,7 +44,8 @@
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -52,7 +53,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static inline int spd_read_byte(u32 device, u32 address)
 {
-	return smbus_read_byte(device, address);
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
 #include "northbridge/amd/amdk8/amdk8.h"
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index 7ed615dd5b..2cbeaf127b 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -25,11 +25,10 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-#define SMBUS_IO_BASE 0x6000
-
 uint64_t uma_memory_base, uma_memory_size;
 
 void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 680e60dbb7..4d26ca392a 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -48,7 +48,8 @@
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdfam10/debug.c"
 #include <spd.h>
 
@@ -56,7 +57,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
 {
-	return smbus_read_byte(device, address);
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
@@ -73,7 +74,6 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/early_setup.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig
index b18115b8e9..e9d6081912 100644..100755
--- a/src/mainboard/amd/tilapia_fam10/Kconfig
+++ b/src/mainboard/amd/tilapia_fam10/Kconfig
@@ -83,4 +83,13 @@ config RAMBASE
 	hex
 	default 0x200000
 
+config VGA_BIOS
+        bool
+        default n
+
+config VGA_BIOS_ID
+        string
+        depends on VGA_BIOS
+        default "1002,9615"
+
 endif # BOARD_AMD_TILAPIA_FAM10
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index 84ff92884c..357bdac230 100644..100755
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -26,15 +26,12 @@
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
 #define ADT7461_ADDRESS 0x4C
 #define ARA_ADDRESS     0x0C /* Alert Response Address */
 
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
-			       u8 val);
-
 #define ADT7461_read_byte(address) \
 	do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
 #define ARA_read_byte(address) \
@@ -42,8 +39,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-#define SMBUS_IO_BASE 0x6000
-
 uint64_t uma_memory_base, uma_memory_size;
 
 void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 3a85a15f84..48b13be1c7 100644..100755
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -48,14 +48,15 @@
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
 {
-	return smbus_read_byte(device, address);
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"