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-rw-r--r--src/mainboard/amd/bettong/Kconfig1
-rw-r--r--src/mainboard/amd/bettong/romstage.c2
-rw-r--r--src/mainboard/amd/db-ft3b-lc/Kconfig1
-rw-r--r--src/mainboard/amd/db-ft3b-lc/romstage.c2
-rw-r--r--src/mainboard/amd/lamar/Kconfig1
-rw-r--r--src/mainboard/amd/lamar/romstage.c2
-rw-r--r--src/mainboard/amd/olivehill/Kconfig1
-rw-r--r--src/mainboard/amd/olivehill/romstage.c2
-rw-r--r--src/mainboard/amd/olivehillplus/Kconfig1
-rw-r--r--src/mainboard/amd/olivehillplus/romstage.c2
-rw-r--r--src/mainboard/amd/parmer/Kconfig1
-rw-r--r--src/mainboard/amd/parmer/romstage.c2
-rw-r--r--src/mainboard/amd/thatcher/Kconfig1
-rw-r--r--src/mainboard/amd/thatcher/romstage.c1
14 files changed, 7 insertions, 13 deletions
diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig
index f5f37cef77..08410d3a72 100644
--- a/src/mainboard/amd/bettong/Kconfig
+++ b/src/mainboard/amd/bettong/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
select CPU_AMD_PI_00660F01
select NORTHBRIDGE_AMD_PI_00660F01
select SOUTHBRIDGE_AMD_PI_KERN
+ select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index c9a257cec5..58430dcf17 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -29,8 +29,6 @@ static void romstage_main_template(void)
{
u32 val;
- hudson_lpc_port80();
-
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig
index b83a5253d2..eb5fe8786f 100644
--- a/src/mainboard/amd/db-ft3b-lc/Kconfig
+++ b/src/mainboard/amd/db-ft3b-lc/Kconfig
@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS
select CPU_AMD_PI_00730F01
select NORTHBRIDGE_AMD_PI_00730F01
select SOUTHBRIDGE_AMD_PI_AVALON
+ select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index 475431e419..a0c6b8d9f3 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -37,8 +37,6 @@ static void romstage_main_template(void)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- hudson_lpc_port80();
-
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig
index 1d3e0f66a7..d509afcfa9 100644
--- a/src/mainboard/amd/lamar/Kconfig
+++ b/src/mainboard/amd/lamar/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
select CPU_AMD_PI_00630F01
select NORTHBRIDGE_AMD_PI_00630F01
select SOUTHBRIDGE_AMD_PI_BOLTON
+ select DEFAULT_POST_ON_LPC
select SUPERIO_FINTEK_F81216H
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 4dde4e2e3f..7f37990efc 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -48,8 +48,6 @@ static void romstage_main_template(void)
*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
- hudson_lpc_port80();
-
if (!cpu_init_detectedx) {
post_code(0x30);
f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777);
diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig
index 806fdbd1d8..e1b5215348 100644
--- a/src/mainboard/amd/olivehill/Kconfig
+++ b/src/mainboard/amd/olivehill/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
select CPU_AMD_AGESA_FAMILY16_KB
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 9a28f98b33..122bb19e3d 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -41,8 +41,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80();
-
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
for (i = 0; i < 200000; i++)
val = inb(0xcd6);
diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig
index 230dc4b25d..229e3f97e0 100644
--- a/src/mainboard/amd/olivehillplus/Kconfig
+++ b/src/mainboard/amd/olivehillplus/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
select CPU_AMD_PI_00730F01
select NORTHBRIDGE_AMD_PI_00730F01
select SOUTHBRIDGE_AMD_PI_AVALON
+ select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index bb80687b60..c04aafeff6 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -37,8 +37,6 @@ static void romstage_main_template(void)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- hudson_lpc_port80();
-
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig
index dde58a6fd4..3b6cb5ce89 100644
--- a/src/mainboard/amd/parmer/Kconfig
+++ b/src/mainboard/amd/parmer/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
select CPU_AMD_AGESA_FAMILY15_TN
select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 48aee89a9b..6366c4e348 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -19,8 +19,6 @@
void board_BeforeAgesa(struct sysinfo *cb)
{
- hudson_lpc_port80();
-
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
/* For serial port option, plug-in card on LPC. */
diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig
index e11d0ea1d9..2c0939c84e 100644
--- a/src/mainboard/amd/thatcher/Kconfig
+++ b/src/mainboard/amd/thatcher/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
select CPU_AMD_AGESA_FAMILY15_TN
select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 1d89e4d6d1..5678021f8b 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -31,7 +31,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
/* Set LPC decode enables. */
dev = PCI_DEV(0, 0x14, 3);
- hudson_lpc_port80();
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 15:40:54 +0000