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-rw-r--r--src/mainboard/amd/onyx/devicetree.cb4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb
index 3d63da586b..80c25e1899 100644
--- a/src/mainboard/amd/onyx/devicetree.cb
+++ b/src/mainboard/amd/onyx/devicetree.cb
@@ -53,6 +53,7 @@ chip soc/amd/genoa
}"
device domain 0 on
+ device ref iommu_0 on end
device ref gpp_bridge_0_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P2
register "start_lane" = "48"
@@ -84,6 +85,7 @@ chip soc/amd/genoa
end
device domain 1 on
+ device ref iommu_1 on end
device ref gpp_bridge_1_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P3
register "start_lane" = "16"
@@ -105,6 +107,7 @@ chip soc/amd/genoa
end
device domain 2 on
+ device ref iommu_2 on end
device ref gpp_bridge_2_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P1
register "start_lane" = "32"
@@ -128,6 +131,7 @@ chip soc/amd/genoa
end
device domain 3 on
+ device ref iommu_3 on end
device ref gpp_bridge_3_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P0
register "start_lane" = "0"