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-rw-r--r--src/mainboard/amd/mandolin/Kconfig13
-rw-r--r--src/mainboard/amd/mandolin/Kconfig.name3
-rw-r--r--src/mainboard/amd/mandolin/Makefile.inc4
-rw-r--r--src/mainboard/amd/mandolin/variants/cereme/board.fmd8
-rw-r--r--src/mainboard/amd/mandolin/variants/cereme/devicetree.cb184
-rw-r--r--src/mainboard/amd/mandolin/variants/cereme/early_gpio.c32
-rw-r--r--src/mainboard/amd/mandolin/variants/cereme/gpio.c33
-rw-r--r--src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c87
8 files changed, 362 insertions, 2 deletions
diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig
index 63b6306df8..8e2bd8ba28 100644
--- a/src/mainboard/amd/mandolin/Kconfig
+++ b/src/mainboard/amd/mandolin/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-if BOARD_AMD_MANDOLIN
+if BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_AMD_PICASSO
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN
+ select BOARD_ROMSIZE_KB_16384 if BOARD_AMD_CEREME
select AZALIA_PLUGIN_SUPPORT
select HAVE_ACPI_RESUME
select DRIVERS_UART_ACPI
@@ -31,6 +32,7 @@ config AMD_LPC_DEBUG_CARD
config CBFS_SIZE
hex
default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP
+ default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP
config MAINBOARD_DIR
string
@@ -39,10 +41,12 @@ config MAINBOARD_DIR
config VARIANT_DIR
string
default "mandolin" if BOARD_AMD_MANDOLIN
+ default "cereme" if BOARD_AMD_CEREME
config MAINBOARD_PART_NUMBER
string
default "MANDOLIN" if BOARD_AMD_MANDOLIN
+ default "CEREME" if BOARD_AMD_CEREME
config DEVICETREE
string
@@ -59,6 +63,7 @@ config ONBOARD_VGA_IS_PRIMARY
config AMD_FWM_POSITION_INDEX
int
default 3 if BOARD_AMD_MANDOLIN
+ default 4 if BOARD_AMD_CEREME
help
TODO: might need to be adapted for better placement of files in cbfs
@@ -70,6 +75,7 @@ config MANDOLIN_MCHP_FW_FILE
string
depends on MANDOLIN_HAVE_MCHP_FW
default "3rdparty/blobs/mainboard/amd/mandolin/EC_mandolin.bin" if BOARD_AMD_MANDOLIN
+ default "3rdparty/blobs/mainboard/amd/mandolin/EC_cereme.bin" if BOARD_AMD_CEREME
if !AMD_LPC_DEBUG_CARD
choice
@@ -106,19 +112,22 @@ config VGA_BIOS_DGPU_ID
config VGA_BIOS_DGPU_FILE
string
default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN
+ default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" if BOARD_AMD_CEREME
config EFS_SPI_READ_MODE
int
default 0 if EM100
+ default 0 if BOARD_AMD_CEREME
default 3
config EFS_SPI_SPEED
int
default 3 if EM100
+ default 1 if BOARD_AMD_CEREME
default 0
config EFS_SPI_MICRON_FLAG
int
default 0
-endif # BOARD_AMD_MANDOLIN
+endif # BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME
diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name
index 7dbfc3fd71..6f512337a3 100644
--- a/src/mainboard/amd/mandolin/Kconfig.name
+++ b/src/mainboard/amd/mandolin/Kconfig.name
@@ -1,2 +1,5 @@
config BOARD_AMD_MANDOLIN
bool "Mandolin"
+
+config BOARD_AMD_CEREME
+ bool "Cereme"
diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc
index 6d7bf3a8b9..778701834f 100644
--- a/src/mainboard/amd/mandolin/Makefile.inc
+++ b/src/mainboard/amd/mandolin/Makefile.inc
@@ -10,7 +10,11 @@ ifneq ($(CONFIG_PICASSO_LPC_IOMUX),y)
ramstage-y += emmc_gpio.c
endif
+ifeq ($(CONFIG_BOARD_AMD_MANDOLIN),y)
APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_mandolin.bin
+else # CONFIG_BOARD_AMD_CEREME
+APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_cereme.bin
+endif
PHONY+=add_mchp_fw
INTERMEDIATE+=add_mchp_fw
diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd
new file mode 100644
index 0000000000..b55b8b506a
--- /dev/null
+++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd
@@ -0,0 +1,8 @@
+FLASH@0xFF000000 16M {
+ BIOS {
+ EC 0x20000
+ RW_MRC_CACHE 0x10000
+ FMAP 0x1000
+ COREBOOT(CBFS)
+ }
+}
diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
new file mode 100644
index 0000000000..155328871c
--- /dev/null
+++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
@@ -0,0 +1,184 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/amd/picasso
+ register "acp_pin_cfg" = "I2S_PINS_MAX_HDA"
+
+ # Set FADT Configuration
+ register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
+ register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec
+
+ register "emmc_config" = "{
+ .timing = SD_EMMC_DISABLE,
+ }"
+
+ register "has_usb2_phy_tune_params" = "1"
+
+ # Controller0 Port0 Default
+ register "usb_2_port_tune_params[0]" = "{
+ .com_pds_tune = 0x03,
+ .sq_rx_tune = 0x3,
+ .tx_fsls_tune = 0x3,
+ .tx_pre_emp_amp_tune = 0x03,
+ .tx_pre_emp_pulse_tune = 0x0,
+ .tx_rise_tune = 0x1,
+ .rx_vref_tune = 0x6,
+ .tx_hsxv_tune = 0x3,
+ .tx_res_tune = 0x01,
+ }"
+
+ # Controller0 Port1 Default
+ register "usb_2_port_tune_params[1]" = "{
+ .com_pds_tune = 0x03,
+ .sq_rx_tune = 0x3,
+ .tx_fsls_tune = 0x3,
+ .tx_pre_emp_amp_tune = 0x03,
+ .tx_pre_emp_pulse_tune = 0x0,
+ .tx_rise_tune = 0x1,
+ .rx_vref_tune = 0x6,
+ .tx_hsxv_tune = 0x3,
+ .tx_res_tune = 0x01,
+ }"
+
+ # Controller0 Port2 Default
+ register "usb_2_port_tune_params[2]" = "{
+ .com_pds_tune = 0x03,
+ .sq_rx_tune = 0x3,
+ .tx_fsls_tune = 0x3,
+ .tx_pre_emp_amp_tune = 0x03,
+ .tx_pre_emp_pulse_tune = 0x0,
+ .tx_rise_tune = 0x1,
+ .rx_vref_tune = 0x6,
+ .tx_hsxv_tune = 0x3,
+ .tx_res_tune = 0x01,
+ }"
+
+ # Controller0 Port3 Default
+ register "usb_2_port_tune_params[3]" = "{
+ .com_pds_tune = 0x03,
+ .sq_rx_tune = 0x3,
+ .tx_fsls_tune = 0x3,
+ .tx_pre_emp_amp_tune = 0x03,
+ .tx_pre_emp_pulse_tune = 0x0,
+ .tx_rise_tune = 0x1,
+ .rx_vref_tune = 0x6,
+ .tx_hsxv_tune = 0x3,
+ .tx_res_tune = 0x01,
+ }"
+
+ # Controller0 Port4 Default
+ register "usb_2_port_tune_params[4]" = "{
+ .com_pds_tune = 0x03,
+ .sq_rx_tune = 0x3,
+ .tx_fsls_tune = 0x3,
+ .tx_pre_emp_amp_tune = 0x02,
+ .tx_pre_emp_pulse_tune = 0x0,
+ .tx_rise_tune = 0x1,
+ .rx_vref_tune = 0x5,
+ .tx_hsxv_tune = 0x3,
+ .tx_res_tune = 0x01,
+ }"
+
+ # Controller0 Port5 Default
+ register "usb_2_port_tune_params[5]" = "{
+ .com_pds_tune = 0x03,
+ .sq_rx_tune = 0x3,
+ .tx_fsls_tune = 0x3,
+ .tx_pre_emp_amp_tune = 0x02,
+ .tx_pre_emp_pulse_tune = 0x0,
+ .tx_rise_tune = 0x1,
+ .rx_vref_tune = 0x5,
+ .tx_hsxv_tune = 0x3,
+ .tx_res_tune = 0x01,
+ }"
+
+ # USB OC pin mapping; all ports share one OC pin
+ register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0"
+ register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0"
+ register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0"
+ register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0"
+ register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0"
+ register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0"
+
+ # SPI Configuration
+ register "common_config.spi_config" = "{
+ .normal_speed = SPI_SPEED_33M, /* MHz */
+ .fast_speed = SPI_SPEED_66M, /* MHz */
+ .altio_speed = SPI_SPEED_33M, /* MHz */
+ .tpm_speed = SPI_SPEED_33M, /* MHz */
+ .read_mode = SPI_READ_MODE_QUAD114,
+ }"
+
+ # eSPI Configuration
+ register "common_config.espi_config" = "{
+ .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN,
+ .generic_io_range[0] = {
+ .base = 0x662,
+ .size = 8,
+ },
+
+ .io_mode = ESPI_IO_MODE_SINGLE,
+ .op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
+ .crc_check_enable = 1,
+ .dedicated_alert_pin = 1,
+ .periph_ch_en = 0,
+ .vw_ch_en = 0,
+ .oob_ch_en = 0,
+ .flash_ch_en = 0,
+ }"
+
+ # genral purpose PCIe clock output configuration
+ register "gpp_clk_config[0]" = "GPP_CLK_REQ"
+ register "gpp_clk_config[1]" = "GPP_CLK_REQ"
+ register "gpp_clk_config[2]" = "GPP_CLK_REQ"
+ register "gpp_clk_config[3]" = "GPP_CLK_OFF"
+ register "gpp_clk_config[4]" = "GPP_CLK_REQ"
+ register "gpp_clk_config[5]" = "GPP_CLK_OFF"
+ register "gpp_clk_config[6]" = "GPP_CLK_OFF"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ subsystemid 0x1022 0x1510 inherit
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 on end # IOMMU
+ device pci 1.0 on end # Dummy Host Bridge
+ device pci 1.1 on end # Bridge to PCIe Ethernet chip
+ device pci 8.0 on end # Dummy Host Bridge
+ device pci 8.1 on # Bridge to Bus A
+ device pci 0.0 on end # Internal GPU
+ device pci 0.1 on end # Display HDA
+ device pci 0.2 on end # Crypto Coprocessor
+ device pci 0.3 on end # USB 3.1
+ device pci 0.4 off end # USB 3.1
+ device pci 0.5 on end # Audio
+ device pci 0.6 on end # HDA
+ device pci 0.7 on end # non-Sensor Fusion Hub device
+ end
+ device pci 8.2 on # Bridge to Bus B
+ device pci 0.0 off end # AHCI
+ device pci 0.1 off end # integrated Ethernet MAC
+ device pci 0.2 off end # integrated Ethernet MAC
+ end
+ device pci 14.0 on end # SMBus
+ device pci 14.3 on # D14F3 bridge
+ chip superio/smsc/sio1036 # optional debug card
+ end
+ end
+ device pci 14.6 off end # SDHCI
+ device pci 18.0 on end # Data fabric [0-7]
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+ device pci 18.6 on end
+ device pci 18.7 on end
+ end # domain
+
+ device mmio 0xfedc9000 on end # UART0
+ device mmio 0xfedca000 on end # UART1
+ device mmio 0xfedce000 off end # UART2
+ device mmio 0xfedcf000 off end # UART3
+
+end # chip soc/amd/picasso
diff --git a/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c b/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c
new file mode 100644
index 0000000000..b4ee5f485a
--- /dev/null
+++ b/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../gpio.h"
+
+/* GPIO pins used by coreboot should be initialized in bootblock */
+
+static const struct soc_amd_gpio gpio_set_stage_reset[] = {
+ /* not LLB */
+ PAD_GPI(GPIO_12, PULL_UP),
+ /* not USB_OC1_L */
+ PAD_GPI(GPIO_17, PULL_UP),
+ /* not USB_OC2_L */
+ PAD_GPI(GPIO_18, PULL_UP),
+ /* SDIO eMMC power control */
+ PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE),
+ /* PCIe Reset 0 */
+ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
+ /* PCIe Reset 1 */
+ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
+ /* eSPI CS# */
+ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
+ /* FANOUT0 */
+ PAD_NF(GPIO_85, FANOUT0, PULL_NONE),
+ /* PC beep to codec */
+ PAD_NF(GPIO_91, SPKR, PULL_NONE),
+};
+
+void mainboard_program_early_gpios(void)
+{
+ program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
+}
diff --git a/src/mainboard/amd/mandolin/variants/cereme/gpio.c b/src/mainboard/amd/mandolin/variants/cereme/gpio.c
new file mode 100644
index 0000000000..0ba2580ce1
--- /dev/null
+++ b/src/mainboard/amd/mandolin/variants/cereme/gpio.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../gpio.h"
+
+/*
+ * As a rule of thumb, GPIO pins used by coreboot should be initialized at
+ * bootblock while GPIO pins used only by the OS should be initialized at
+ * ramstage.
+ */
+static const struct soc_amd_gpio gpio_set_stage_ram[] = {
+ /* EC SCI# */
+ PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW),
+ /* I2S SDIN */
+ PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
+ /* I2S LRCLK */
+ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
+ /* not Blink */
+ PAD_GPI(GPIO_11, PULL_UP),
+ /* APU_ALS_INT# */
+ PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
+ /* SD card detect */
+ PAD_GPI(GPIO_31, PULL_UP),
+ /* NFC IRQ */
+ PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS),
+ /* NFC wake output# */
+ PAD_GPO(GPIO_89, HIGH),
+};
+
+void mainboard_program_gpios(void)
+{
+ program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
+}
diff --git a/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c
new file mode 100644
index 0000000000..8fc94f8c3b
--- /dev/null
+++ b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/platform_descriptors.h>
+#include <types.h>
+
+static const fsp_dxio_descriptor pollock_dxio_descriptors[] = {
+ { /* NVME SSD */
+ .port_present = true,
+ .engine_type = PCIE_ENGINE,
+ .start_logical_lane = 0,
+ .end_logical_lane = 0,
+ .device_number = 1,
+ .function_number = 3,
+ .link_aspm = ASPM_L1,
+ .link_aspm_L1_1 = true,
+ .link_aspm_L1_2 = true,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ0
+ },
+ { /* WWAN */
+ .port_present = true,
+ .engine_type = PCIE_ENGINE,
+ .start_logical_lane = 1,
+ .end_logical_lane = 1,
+ .device_number = 1,
+ .function_number = 4,
+ .link_aspm = ASPM_L1,
+ .link_aspm_L1_1 = true,
+ .link_aspm_L1_2 = true,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ2
+ },
+ { /* LAN */
+ .port_present = true,
+ .engine_type = PCIE_ENGINE,
+ .start_logical_lane = 4,
+ .end_logical_lane = 4,
+ .device_number = 1,
+ .function_number = 1,
+ .link_aspm = ASPM_L1,
+ .link_aspm_L1_1 = true,
+ .link_aspm_L1_2 = true,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ1
+ },
+ { /* WLAN */
+ .port_present = true,
+ .engine_type = PCIE_ENGINE,
+ .start_logical_lane = 5,
+ .end_logical_lane = 5,
+ .device_number = 1,
+ .function_number = 2,
+ .link_aspm = ASPM_L1,
+ .link_aspm_L1_1 = true,
+ .link_aspm_L1_2 = true,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ4
+ }
+};
+
+fsp_ddi_descriptor pollock_ddi_descriptors[] = {
+ { /* DDI0 - eDP */
+ .connector_type = EDP,
+ .aux_index = AUX1,
+ .hdp_index = HDP1
+ },
+ { /* DDI1 - DP */
+ .connector_type = DP,
+ .aux_index = AUX2,
+ .hdp_index = HDP2
+ },
+ { /* DDI2 - DP */
+ .connector_type = DP,
+ .aux_index = AUX4,
+ .hdp_index = HDP4,
+ }
+};
+
+void mainboard_get_dxio_ddi_descriptors(
+ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
+ const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
+{
+ *dxio_descs = pollock_dxio_descriptors;
+ *dxio_num = ARRAY_SIZE(pollock_dxio_descriptors);
+ *ddi_descs = pollock_ddi_descriptors;
+ *ddi_num = ARRAY_SIZE(pollock_ddi_descriptors);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 22:16:19 +0000