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-rw-r--r--src/mainboard/amd/solo/auto.c29
-rw-r--r--src/mainboard/amd/solo/mptable.c4
2 files changed, 15 insertions, 18 deletions
diff --git a/src/mainboard/amd/solo/auto.c b/src/mainboard/amd/solo/auto.c
index 33dea8e80d..e8e3976ef2 100644
--- a/src/mainboard/amd/solo/auto.c
+++ b/src/mainboard/amd/solo/auto.c
@@ -20,7 +20,9 @@ static int boot_cpu(void)
msr = rdmsr(0x1b);
bsp = !!(msr.lo & (1 << 8));
if (bsp) {
- print_debug("Bootstrap cpu\r\n");
+ print_debug("Bootstrap processor\r\n");
+ } else {
+ print_debug("Application processor\r\n");
}
return bsp;
@@ -110,14 +112,19 @@ static void dump_spd_registers(void)
}
}
-
-
-
static void main(void)
{
uart_init();
console_init();
+#if 0
+ print_debug(" XIP_ROM_BASE: ");
+ print_debug_hex32(XIP_ROM_BASE);
+ print_debug(" XIP_ROM_SIZE: ");
+ print_debug_hex32(XIP_ROM_SIZE);
+ print_debug("\r\n");
+#endif
if (boot_cpu() && !cpu_init_detected()) {
+ setup_default_resource_map();
setup_coherent_ht_domain();
enumerate_ht_chain();
print_pci_devices();
@@ -125,17 +132,7 @@ static void main(void)
sdram_initialize();
dump_spd_registers();
-#if 0
- ram_fill( 0x00100000, 0x00180000);
- ram_verify(0x00100000, 0x00180000);
-#endif
-#ifdef MEMORY_1024MB
- ram_fill( 0x00000000, 0x00001000);
- ram_verify(0x00000000, 0x00001000);
-#endif
-#ifdef MEMROY_512MB
- ram_fill( 0x00000000, 0x01ffffff);
- ram_verify(0x00000000, 0x01ffffff);
-#endif
+ /* Check the first 8M */
+ ram_check(0x00100000, 0x00800000);
}
}
diff --git a/src/mainboard/amd/solo/mptable.c b/src/mainboard/amd/solo/mptable.c
index 656b790035..49cd1951e6 100644
--- a/src/mainboard/amd/solo/mptable.c
+++ b/src/mainboard/amd/solo/mptable.c
@@ -7,8 +7,8 @@
void *smp_write_config_table(void *v, unsigned long * processor_map)
{
static const char sig[4] = "PCMP";
- static const char oem[8] = "LNXI ";
- static const char productid[12] = "P4DPR ";
+ static const char oem[8] = "AMD ";
+ static const char productid[12] = "SOLO7 ";
struct mp_config_table *mc;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);