5 files changed, 2 insertions, 11 deletions
diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 510b8f86f0..33ca9a2210 100644
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -33,7 +33,6 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-#define POST_CODE(x) outb(x, 0x80)
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
@@ -98,7 +97,7 @@ static void mb_gpio_init(void)
 
 void cache_as_ram_main(void)
 {
-	POST_CODE(0x01);
+	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
 		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 3c808d41cb..676ce4ef9c 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -45,8 +45,6 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 
-#define post_code(x) outb(x, 0x80)
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 3dc2801546..97c198895d 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -45,8 +45,6 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 
-#define post_code(x) outb(x, 0x80)
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index 8c17b0affa..d742f50026 100644
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -32,8 +32,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 
-#define POST_CODE(x) outb(x, 0x80)
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
@@ -95,7 +93,7 @@ static void mb_gpio_init(void)
 
 void cache_as_ram_main(void)
 {
-	POST_CODE(0x01);
+	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
 		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 6cdaf42df5..a3a34d6987 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -39,8 +39,6 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 
-#define post_code(x) outb(x, 0x80)
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"