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-rw-r--r--src/mainboard/amd/quartet/Config.lb35
-rw-r--r--src/mainboard/amd/quartet/auto.c2
-rw-r--r--src/mainboard/amd/quartet/mainboard.c2
-rw-r--r--src/mainboard/amd/solo/Config.lb71
-rw-r--r--src/mainboard/amd/solo/mainboard.c2
5 files changed, 15 insertions, 97 deletions
diff --git a/src/mainboard/amd/quartet/Config.lb b/src/mainboard/amd/quartet/Config.lb
index 97634ab25a..b6d65b4cb5 100644
--- a/src/mainboard/amd/quartet/Config.lb
+++ b/src/mainboard/amd/quartet/Config.lb
@@ -1,8 +1,6 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
-uses USE_NORMAL_IMAGE
-uses ENABLE_IOMMU
#
#
###
@@ -34,15 +32,11 @@ ldscript /cpu/i386/entry32.lds
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/i386/reset16.inc
+ ldscript /cpu/i386/reset16.lds
else
- print "NO FALLBACK USED!"
-end
-
-if USE_NORMAL_IMAGE
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/i386/reset32.inc
+ ldscript /cpu/i386/reset32.lds
end
#
#### Should this be in the northbridge code?
@@ -76,15 +70,6 @@ end
mainboardinit cpu/k8/earlymtrr.inc
#
#
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
-###
-#
-if USE_FALLBACK_IMAGE
- mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
-end
-#
####
#### O.k. We aren't just an intermediary anymore!
####
@@ -94,10 +79,6 @@ end
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
-#if DISABLE_WATCHDOG
-# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
-#end
#
if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#
@@ -118,13 +99,6 @@ end
mainboardinit ./auto.inc
#
###
-### Setup RAM
-###
-mainboardinit ram/ramtest.inc
-mainboardinit southbridge/amd/amd8111/smbus.inc
-mainboardinit sdram/generic_dump_spd.inc
-#
-###
### Include the secondary Configuration files
###
northbridge amd/amdk8
@@ -142,4 +116,3 @@ cpu p6 end
cpu k7 end
cpu k8 end
-option ENABLE_IOMMU=1
diff --git a/src/mainboard/amd/quartet/auto.c b/src/mainboard/amd/quartet/auto.c
index a347f20b70..3166f7ad3c 100644
--- a/src/mainboard/amd/quartet/auto.c
+++ b/src/mainboard/amd/quartet/auto.c
@@ -17,6 +17,8 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
+#define SIO_BASE 0x2e
+
static void memreset_setup(void)
{
/* Set the memreset low */
diff --git a/src/mainboard/amd/quartet/mainboard.c b/src/mainboard/amd/quartet/mainboard.c
index d93d2ed1d9..0622150d64 100644
--- a/src/mainboard/amd/quartet/mainboard.c
+++ b/src/mainboard/amd/quartet/mainboard.c
@@ -5,7 +5,7 @@
#include <device/pci_ops.h>
-unsigned long initial_apicid[MAX_CPUS] =
+unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0, 1, 2, 3
};
diff --git a/src/mainboard/amd/solo/Config.lb b/src/mainboard/amd/solo/Config.lb
index f237a5cbea..12c59fdb38 100644
--- a/src/mainboard/amd/solo/Config.lb
+++ b/src/mainboard/amd/solo/Config.lb
@@ -24,8 +24,6 @@ default CONFIG_UDELAY_TSC=0
###
### Customize our winbond superio chip for this motherboard
###
-option SIO_BASE=0x2e
-option SIO_SYSTEM_CLK_INPUT=0
option CONFIG_CONSOLE_SERIAL8250=0
#
###
@@ -51,16 +49,11 @@ option IRQ_SLOT_COUNT=7
##option HAVE_MP_TABLE=1
#
###
-### Do not build special code for the keyboard
-###
-default NO_KEYBOARD=1
-#
-###
### Build code for SMP support
### Only worry about 2 micro processors
###
##option CONFIG_SMP=1
-option MAX_CPUS=1
+option CONFIG_MAX_CPUS=1
#
###
### Build code to setup a generic IOAPIC
@@ -79,37 +72,17 @@ option CONFIG_IOAPIC=1
option MEMORY_HOLE=0
#
###
-### Enable both fixed and variable MTRRS
-### When we setup MTRRs in mtrr.c
-###
-### We must setup the fixed mtrrs or we confuse SMP secondary
-### processor identification
-###
-option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
-#
-###
### Clean up the motherboard id strings
###
option MAINBOARD_PART_NUMBER="Solo7"
option MAINBOARD_VENDOR="AMD"
#
###
-### Let Assembly code know where on the pci bus the AMD southbridge is
-###
-option AMD8111_DEV=0x3800
-#
-###
-### Call the final_mainboard_fixup function
-###
-option FINAL_MAINBOARD_FIXUP=1
-#
-###
### Figure out which type of linuxBIOS image to build
### If we aren't a fallback image we must be a normal image
### This is useful for optional includes
###
default USE_FALLBACK_IMAGE=0
-option USE_NORMAL_IMAGE=(! USE_FALLBACK_IMAGE)
#
####
#### LinuxBIOS layout values
@@ -144,8 +117,7 @@ default FALLBACK_SIZE=65536
if USE_FALLBACK_IMAGE
option ROM_SECTION_SIZE = FALLBACK_SIZE
option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
-end
-if USE_NORMAL_IMAGE
+else
option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
option ROM_SECTION_OFFSET= 0
end
@@ -177,13 +149,6 @@ option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
##option XIP_ROM_BASE=0xffff8000
#
###
-### Compute where the SMP startup code needs to live
-### FIXME I don't see how to make this work for the normal image....
-###
-option START_CPU_SEG=0xf0000
-#
-#
-###
### Set all of the defaults for an x86 architecture
###
#
@@ -217,13 +182,11 @@ ldscript /cpu/i386/entry32.lds
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
-end
-
-if USE_NORMAL_IMAGE
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/i386/reset16.inc
+ ldscript /cpu/i386/reset16.lds
+else
+ mainboardinit cpu/i386/reset32.inc
+ ldscript /cpu/i386/reset32.lds
end
#
#### Should this be in the northbridge code?
@@ -251,15 +214,6 @@ end
mainboardinit cpu/k8/earlymtrr.inc
#
#
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
-###
-#
-if USE_FALLBACK_IMAGE
- mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
-end
-#
####
#### O.k. We aren't just an intermediary anymore!
####
@@ -269,10 +223,6 @@ end
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
-#if DISABLE_WATCHDOG
-# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
-#end
#
###
### Setup the serial port
@@ -293,13 +243,6 @@ makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
mainboardinit ./auto.inc
#
###
-### Setup RAM
-###
-mainboardinit ram/ramtest.inc
-mainboardinit southbridge/amd/amd8111/smbus.inc
-mainboardinit sdram/generic_dump_spd.inc
-#
-###
### Include the secondary Configuration files
###
northbridge amd/amdk8
diff --git a/src/mainboard/amd/solo/mainboard.c b/src/mainboard/amd/solo/mainboard.c
index 5690bd5afd..75a77d6adb 100644
--- a/src/mainboard/amd/solo/mainboard.c
+++ b/src/mainboard/amd/solo/mainboard.c
@@ -5,7 +5,7 @@
#include <device/pci_ops.h>
-unsigned long initial_apicid[MAX_CPUS] =
+unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
0
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 19:43:35 +0000