diff options
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/amd/db800/devicetree.cb | 68 | ||||
| -rw-r--r-- | src/mainboard/amd/dbm690t/devicetree.cb | 117 | ||||
| -rw-r--r-- | src/mainboard/amd/norwich/devicetree.cb | 41 | ||||
| -rw-r--r-- | src/mainboard/amd/pistachio/devicetree.cb | 77 | ||||
| -rw-r--r-- | src/mainboard/amd/rumba/devicetree.cb | 21 | ||||
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah/Kconfig | 49 | ||||
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah/Makefile.inc | 95 | ||||
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah/devicetree.cb | 159 | ||||
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb | 152 |
10 files changed, 780 insertions, 0 deletions
diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig new file mode 100644 index 0000000000..f16f5e1dca --- /dev/null +++ b/src/mainboard/amd/Kconfig @@ -0,0 +1 @@ +source "src/mainboard/amd/serengeti_cheetah/Kconfig"
\ No newline at end of file diff --git a/src/mainboard/amd/db800/devicetree.cb b/src/mainboard/amd/db800/devicetree.cb new file mode 100644 index 0000000000..d79fb51c2c --- /dev/null +++ b/src/mainboard/amd/db800/devicetree.cb @@ -0,0 +1,68 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci d.0 on end # Ethernet + device pci e.0 on end # Slot1 + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # Com2 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off end # HW Monitor + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end + diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb new file mode 100644 index 0000000000..d873681351 --- /dev/null +++ b/src/mainboard/amd/dbm690t/devicetree.cb @@ -0,0 +1,117 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_S1G1 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + chip drivers/pci/onboard + device pci 5.0 on end # Internal Graphics 0x791F + register "rom_address" = "0xfff00000" + end + end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "vga_rom_address" = "0xfff00000" + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 + end #pci_domain +end #northbridge/amd/amdk8/root_complex + diff --git a/src/mainboard/amd/norwich/devicetree.cb b/src/mainboard/amd/norwich/devicetree.cb new file mode 100644 index 0000000000..bc08b95954 --- /dev/null +++ b/src/mainboard/amd/norwich/devicetree.cb @@ -0,0 +1,41 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + register "lpc_serirq_enable" = "0x00001002" + register "lpc_serirq_polarity" = "0x0000EFFD" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" #0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "1" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci b.0 on end # Slot 3 + device pci c.0 on end # Slot 4 + device pci d.0 on end # Slot 1 + device pci e.0 on end # Slot 2 + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end + diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb new file mode 100644 index 0000000000..0306417245 --- /dev/null +++ b/src/mainboard/amd/pistachio/devicetree.cb @@ -0,0 +1,77 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_AM2 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge, K8 HT Configuration + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + # device pci 0.1 off end # CLK + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + chip drivers/pci/onboard + device pci 5.0 on end # Internal Graphics 0x791F + register "rom_address" = "0xfff00000" + end + end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "vga_rom_address" = "0xfff00000" + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 off end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 off end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 off end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x438d + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 + + device pci 18.1 on end # K8 Address Map + device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode + device pci 18.3 on end # K8 Miscellaneous Control + end #northbridge/amd/amdk8 + end #pci_domain +end #northbridge/amd/amdk8/root_complex + diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb new file mode 100644 index 0000000000..8c7de64ce7 --- /dev/null +++ b/src/mainboard/amd/rumba/devicetree.cb @@ -0,0 +1,21 @@ +chip northbridge/amd/gx2 + device apic_cluster 0 on + chip cpu/amd/model_gx2 + device apic 0 on end + end + end + device pci_domain 0 on + device pci 1.0 on end + device pci 1.1 on end + chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x80" # enabled with default timing + device pci d.0 on end # Realtek 8139 LAN + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.4 on end # UHCI + end + end +end + diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig new file mode 100644 index 0000000000..bb1571de95 --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -0,0 +1,49 @@ +choice + prompt "Mainboard model" + depends on VENDOR_AMD + +config BOARD_AMD_SERENGETI_CHEETAH + bool "SERENGETI_CHEETAH" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SUPERIO_WINBOND_W83627THF + select PIRQ_TABLE + select MMCONF_SUPPORT + select USE_PRINTK_IN_CAR + help + AMD Serengeti Series mainboards +endchoice + +config MAINBOARD_DIR + string + default amd/serengeti_cheetah + depends on BOARD_AMD_SERENGETI_CHEETAH + +#config DCACHE_RAM_BASE +# hex +# default 0xffdf8000 +# depends on BOARD_AMD_SERENGETI_CHEETAH +# +#config DCACHE_RAM_SIZE +# hex +# default 0x8000 +# depends on BOARD_AMD_SERENGETI_CHEETAH + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_AMD_SERENGETI_CHEETAH + +config LB_CKS_LOC + int + default 123 + depends on BOARD_AMD_SERENGETI_CHEETAH + +config MAINBOARD_PART_NUMBER + string + default "Serengeti-Cheetah" + depends on BOARD_AMD_SERENGETI_CHEETAH diff --git a/src/mainboard/amd/serengeti_cheetah/Makefile.inc b/src/mainboard/amd/serengeti_cheetah/Makefile.inc new file mode 100644 index 0000000000..c54df30683 --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah/Makefile.inc @@ -0,0 +1,95 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +## +## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. +## + +driver-y += mainboard.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o + +#./ssdt.o is in northbridge/amd/amdk8/Config.lb +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS=\ + -DCONFIG_AP_IN_SIPI_WAIT=1 \ + -DCONFIG_USE_PRINTK_IN_CAR=1 \ + -DCONFIG_HAVE_HIGH_TABLES=1 \ + -DCONFIG_MMCONF_SUPPORT=1 \ + -DCONFIG_MMCONF_BASE_ADDRESS=0xf0000000 + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb new file mode 100644 index 0000000000..b9742b4a46 --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb @@ -0,0 +1,159 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8132 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/i2c/i2cmux # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-2-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-2-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-3-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-3-1 + device i2c 57 on end + end + end + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 + device pci 19.0 on # northbridge + chip southbridge/amd/amd8151 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 1.0 on end + end + end # device pci 19.0 + + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + + + end #pci_domain +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end + +end + + diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb new file mode 100644 index 0000000000..71c4daafc1 --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb @@ -0,0 +1,152 @@ +chip northbridge/amd/amdfam10/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F_1207 #L1 and DDR2 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8132 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/i2c/i2cmux2 # pca9556 smbus mux + chip drivers/i2c/i2cmux2 # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + end + end + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end +# device pci 00.5 on end + end + end #pci_domain + #for node 32 to node 63 +# device pci_domain 0 on +# chip northbridge/amd/amdfam10 +# device pci 00.0 on end# northbridge +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.1 on end +# device pci 00.2 on end +# device pci 00.3 on end +# device pci 00.4 on end +# device pci 00.5 on end +# end +# end #pci_domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # hard reset +# device pnp 0.9 off end # mcp55 +# device pnp 0.a on end # GH ext table +# end + +end + + |