diff options
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/inagua/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/amd/persimmon/romstage.c | 7 | ||||
| -rw-r--r-- | src/mainboard/amd/south_station/romstage.c | 7 | ||||
| -rw-r--r-- | src/mainboard/amd/union_station/romstage.c | 7 |
4 files changed, 0 insertions, 27 deletions
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 385328c3d5..151ce31e87 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -40,12 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* all cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 0aad4f5e50..d553c1b52f 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -46,13 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index d37ea0a608..5ef95a0ceb 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -41,13 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index eddcf29fba..cdc564082d 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -39,13 +39,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { |