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-rw-r--r--src/mainboard/amd/union_station/BiosCallOuts.c280
1 files changed, 133 insertions, 147 deletions
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
index ecb7e1cfd6..c701a7e4e2 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.c
+++ b/src/mainboard/amd/union_station/BiosCallOuts.c
@@ -15,6 +15,7 @@
#include <AGESA.h>
#include <amdlib.h>
+#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
@@ -37,166 +38,151 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-/* Call the host environment interface to provide a user hook opportunity. */
+/* Call the host environment interface to provide a user hook opportunity. */
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
- AGESA_STATUS Status;
- UINTN FcnData;
- MEM_DATA_STRUCT *MemData;
- UINT32 AcpiMmioAddr;
- UINT32 GpioMmioAddr;
- UINT8 Data8;
- UINT16 Data16;
- UINT8 TempData8;
+ AGESA_STATUS Status;
+ UINTN FcnData;
+ MEM_DATA_STRUCT *MemData;
+ UINT32 AcpiMmioAddr;
+ UINT32 GpioMmioAddr;
+ UINT8 Data8;
+ UINT8 TempData8;
- FcnData = Data;
- MemData = ConfigPtr;
+ FcnData = Data;
+ MemData = ConfigPtr;
- Status = AGESA_SUCCESS;
- /* Get SB MMIO Base (AcpiMmioAddr) */
- WriteIo8 (0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
- Data16 = Data8 << 8;
- WriteIo8 (0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
- Data16 |= Data8;
- AcpiMmioAddr = (UINT32)Data16 << 16;
- GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+ Status = AGESA_SUCCESS;
+ AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
+ GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
- Data8 &= ~BIT5;
- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- TempData8 &= 0x03;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+ Data8 &= ~BIT5;
+ TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+ TempData8 &= 0x03;
+ TempData8 |= Data8;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
- Data8 |= BIT2+BIT3;
- Data8 &= ~BIT4;
- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- TempData8 &= 0x23;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+ Data8 |= BIT2+BIT3;
+ Data8 &= ~BIT4;
+ TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+ TempData8 &= 0x23;
+ TempData8 |= Data8;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
- Data8 &= ~BIT5;
- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- TempData8 &= 0x03;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+ Data8 &= ~BIT5;
+ TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+ TempData8 &= 0x03;
+ TempData8 |= Data8;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
- Data8 |= BIT2+BIT3;
- Data8 &= ~BIT4;
- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- TempData8 &= 0x23;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+ Data8 |= BIT2+BIT3;
+ Data8 &= ~BIT4;
+ TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+ TempData8 &= 0x23;
+ TempData8 |= Data8;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
- switch(MemData->ParameterListPtr->DDR3Voltage){
- case VOLT1_35:
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- Data8 |= (UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
- break;
- case VOLT1_25:
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
- break;
- case VOLT1_5:
- default:
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- Data8 |= (UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
- }
- return Status;
+ switch (MemData->ParameterListPtr->DDR3Voltage) {
+ case VOLT1_35:
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+ Data8 |= (UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+ break;
+ case VOLT1_25:
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+ break;
+ case VOLT1_5:
+ default:
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+ Data8 |= (UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+ Data8 &= ~(UINT8)BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+ }
+ return Status;
}
/* PCIE slot reset control */
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
- AGESA_STATUS Status;
- UINTN FcnData;
- PCIe_SLOT_RESET_INFO *ResetInfo;
+ AGESA_STATUS Status;
+ UINTN FcnData;
+ PCIe_SLOT_RESET_INFO *ResetInfo;
+ UINT32 GpioMmioAddr;
+ UINT32 AcpiMmioAddr;
+ UINT8 Data8;
- UINT32 GpioMmioAddr;
- UINT32 AcpiMmioAddr;
- UINT8 Data8;
- UINT16 Data16;
-
- FcnData = Data;
- ResetInfo = ConfigPtr;
- // Get SB800 MMIO Base (AcpiMmioAddr)
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
- Data16 = Data8 << 8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
- Data16 |= Data8;
- AcpiMmioAddr = (UINT32)Data16 << 16;
- Status = AGESA_UNSUPPORTED;
- GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
- switch (ResetInfo->ResetId)
- {
- case 4:
- switch (ResetInfo->ResetControl)
- {
- case AssertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
- Status = AGESA_SUCCESS;
- break;
- case DeassertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
- Status = AGESA_SUCCESS;
- break;
- }
- break;
- case 6:
- switch (ResetInfo->ResetControl)
- {
- case AssertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
- Status = AGESA_SUCCESS;
- break;
- case DeassertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
- Status = AGESA_SUCCESS;
- break;
- }
- break;
- case 7:
- switch (ResetInfo->ResetControl)
- {
- case AssertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
- Status = AGESA_SUCCESS;
- break;
- case DeassertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
- Status = AGESA_SUCCESS;
- break;
- }
- break;
- }
- return Status;
+ FcnData = Data;
+ ResetInfo = ConfigPtr;
+ AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
+ GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+ Status = AGESA_UNSUPPORTED;
+ switch (ResetInfo->ResetId) {
+ case 4:
+ switch (ResetInfo->ResetControl) {
+ case AssertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+ Data8 &= ~(UINT8)BIT6;
+ /* MXM_GPIO0. GPIO21 */
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+ Status = AGESA_SUCCESS;
+ break;
+ case DeassertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+ Data8 |= BIT6;
+ /* MXM_GPIO0. GPIO21 */
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+ Status = AGESA_SUCCESS;
+ break;
+ }
+ break;
+ case 6:
+ switch (ResetInfo->ResetControl) {
+ case AssertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+ Data8 &= ~(UINT8)BIT6;
+ /* PCIE_RST#_LAN, GPIO25 */
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+ Status = AGESA_SUCCESS;
+ break;
+ case DeassertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+ Data8 |= BIT6;
+ /* PCIE_RST#_LAN, GPIO25 */
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+ Status = AGESA_SUCCESS;
+ break;
+ }
+ break;
+ case 7:
+ switch (ResetInfo->ResetControl) {
+ case AssertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+ Data8 &= ~(UINT8)BIT6;
+ /* MPCIE_RST0, GPIO02 */
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+ Status = AGESA_SUCCESS;
+ break;
+ case DeassertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+ Data8 |= BIT6;
+ /* MPCIE_RST0, GPIO02 */
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+ Status = AGESA_SUCCESS;
+ break;
+ }
+ break;
+ }
+ return Status;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 22:10:29 +0000