diff options
Diffstat (limited to 'src/mainboard/amd/tilapia_fam10/romstage.c')
| -rw-r--r-- | src/mainboard/amd/tilapia_fam10/romstage.c | 27 |
1 files changed, 6 insertions, 21 deletions
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 1faac4d73f..c68fcccced 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -102,12 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -166,10 +162,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -196,8 +192,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -208,21 +202,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** |