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path: root/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
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Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah_fam10/romstage.c')
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/romstage.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 749b48ede6..76bc73fdb3 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -283,7 +283,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
die("After soft_reset_x - shouldn't see this message!!!\n");
}
@@ -292,7 +292,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* FIXME: Move this to chipset init.
enable cf9 for hard reset */
- print_debug("enable_cf9_x()\n");
+ printk(BIOS_DEBUG, "enable_cf9_x()\n");
enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn);
post_code(0x3C);